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Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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1/1 [
Author: Aaro Koskinen
Email: aaro.koskinen@iki.fi
Subject: MIPS: OCTEON: mangle-port: fix build failure with VDSO code
Date: Tue, 20 Sep 2016 19:54:45 +0800
Patch got from https://patchwork.linux-mips.org/patch/14039/
Commit 1685ddbe35cd ("MIPS: Octeon: Changes to support readq()/writeq()
usage.") added bitwise shift operations that assume that unsigned long
is always 64-bits. This broke the build of VDSO code, as it gets compiled
also in "faked" 32-bit mode. Althought the failing inline functions are
never executed in 32-bit mode, they still need to pass the compilation.
Fix by using 64-bit types explicitly.
The patch fixes the following build failure:
CC arch/mips/vdso/gettimeofday-o32.o
In file included from los/git/devel/linux/arch/mips/include/asm/io.h:32:0,
from los/git/devel/linux/arch/mips/include/asm/page.h:194,
from los/git/devel/linux/arch/mips/vdso/vdso.h:26,
from los/git/devel/linux/arch/mips/vdso/gettimeofday.c:11:
los/git/devel/linux/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h: In function '__should_swizzle_bits':
los/git/devel/linux/arch/mips/include/asm/mach-cavium-octeon/mangle-port.h:19:40: error: right shift count >= width of type [-Werror=shift-count-overflow]
unsigned long did = ((unsigned long)a >> 40) & 0xff;
^~
Fixes: 1685ddbe35cd ("MIPS: Octeon: Changes to support readq()/writeq() usage.")
Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: Kevin Hao <kexin.hao@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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As of v4.6+ this patch is no longer needed to ensure that the
kernel is safely preemptable, so we drop the patch.
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/1 [
Author: Sukadev Bhattiprolu
Email: sukadev@linux.vnet.ibm.com
Subject: perf tools: Fix build break on powerpc
Date: Mon, 28 Mar 2016 17:52:34 -0300
Commit 531d2410635c ("perf tools: Do not include stringify.h from the
kernel sources") seems to have accidentially removed the inclusion of
"util/header.h" from "arch/powerpc/util/header.c".
"util/header.h" provides the prototype for get_cpuid() and is needed to
build perf on Powerpc:
arch/powerpc/util/header.c:17:1: error: no previous prototype for 'get_cpuid' [-Werror=missing-prototypes]
Reported-by: Michael Ellerman <mpe@ellerman.id.au>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Fixes: 531d2410635c ("perf tools: Do not include stringify.h from the kernel sources")
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
[ Included "util.h" too, to get the scnprintf() prototype ]
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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These patches are not appropriate for the dev kernel, so we drop them
until BSP ports can be performed.
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Enable CONFIG_COMPAT for qemuarm64 so 32 bit compatibility is available
for testing.
[YOCTO #8646]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/1 [
Author: Jussi Laako
Email: jussi.laako@linux.intel.com
Subject: gpio-pca953x: add "drive" property
Date: Thu, 10 Mar 2016 11:58:11 -0800
Galileo gen 2 has support for setting GPIO modes. Expose these
properties through the GPIO sysfs interface. This approach is bit hacky,
since it changes the interface semantics.
The original patch was by Josef Ahmad <josef.ahmad@linux.intel.com> and
made on top of kernel 3.8.
Signed-off-by: Ismo Puustinen <ismo.puustinen@intel.com>
Signed-off-by: Jussi Laako <jussi.laako@linux.intel.com>
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/6 [
Author: Ismo Puustinen
Email: ismo.puustinen@intel.com
Subject: acpi: added a custom DSDT file.
Date: Fri, 19 Feb 2016 07:18:25 -0800
The file has fixed GPIO IRQ assignment and moved SPI devices to be under
the SPI bus in the ACPI definitions as assumed by ACPI version 5.
Upstream-status: Inappropriate, custom firmware
Signed-off-by: Ismo Puustinen <ismo.puustinen@intel.com>
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
2/6 [
Author: Andy Shevchenko
Email: andriy.shevchenko@linux.intel.com
Subject: gpio: pca953x: provide GPIO base based on _UID
Date: Fri, 19 Feb 2016 07:18:26 -0800
Custom kernel for Intel Galileo Gen2 provides and moreover libmraa relies on
the continuous GPIO space. To do such we have to configure GPIO base per each
GPIO expander. The only value we can use is the ACPI _UID.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Upstream-status: Inappropriate, custom code for legacy userspace
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
3/6 [
Author: Josef Ahmad
Email: josef.ahmad@linux.intel.com
Subject: pca9685: PCA9685 PWM and GPIO multi-function device.
Date: Fri, 19 Feb 2016 07:18:27 -0800
There is also a driver for the same chip in drivers/pwm. This version
has support for setting the output in GPIO mode in addition to the PWM
mode.
Upstream-status: Forward-ported from Intel IOT Develper Kit Quark BSP.
Inappropriate to the upstream kernel, because the
upstream kernel already uses a different (non-mfd)
driver for handling the same chip, and doesn't need
to be backwards compatible.
Signed-off-by: Ismo Puustinen <ismo.puustinen@intel.com>
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
4/6 [
Author: Ismo Puustinen
Email: ismo.puustinen@intel.com
Subject: spi-pxa2xx: fixed ACPI-based enumeration of SPI devices.
Date: Fri, 19 Feb 2016 07:18:28 -0800
Slave devices were not enumerated by ACPI data because the ACPI handle
for the spi-pxa2xx controller was NULL if it was itself enumerated by
PCI.
Original patch by Mika Westerberg <mika.westerberg@intel.com>.
Upstream-status: Inappropriate, will be fixed with a bigger overhaul of
SPI/ACPI interaction.
Signed-off-by: Ismo Puustinen <ismo.puustinen@intel.com>
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
5/6 [
Author: Todor Minchev
Email: todor@minchev.co.uk
Subject: staging:iio: add support for ADC1x8s102.
Date: Fri, 19 Feb 2016 07:18:29 -0800
Adds new config and support for Texas Instruments ADC1x8S102 driver"
config ADC1x8S102
tristate "Texas Instruments ADC1x8S102 driver"
depends on SPI
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
help
Say yes here to build support for Texas Instruments ADC1x8S102 ADC.
Provides direct access via sysfs.
To compile this driver as a module, choose M here: the module will
be called adc1x8s102
Upstream-status: Forward-ported from Intel IOT Develper Kit Quark BSP
Original author is Bogdan Pricop <bogdan.pricop@emutex.com>.
Signed-off-by: Ismo Puustinen <ismo.puustinen@intel.com>
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
6/6 [
Author: Ismo Puustinen
Email: ismo.puustinen@intel.com
Subject: adc1x8s102: support ACPI-based enumeration.
Date: Fri, 19 Feb 2016 07:18:30 -0800
Upstream-status: Pending for ADC1x8s102 patch upstreaming to Linux kernel
Signed-off-by: Ismo Puustinen <ismo.puustinen@intel.com>
Signed-off-by: Saul Wold <sgw@linux.intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/1 [
Author: Rabin Vincent
Email: rabin.vincent@axis.com
Subject: perf: fix MIPS build
Date: Thu, 28 May 2015 13:46:13 +0200
5e8c0fb6a ("perf build: Add arch x86 objects building") added empty
Build files to several architectures, but MIPS got left out. This leads
to a build of perf for MIPS failing with the following errors:
tools/build/Makefile.build:40: arch/mips/Build: No such file or directory
make[4]: *** No rule to make target `arch/mips/Build'. Stop.
Add an empty Build file to fix this.
Signed-off-by: Rabin Vincent <rabin.vincent@axis.com>
[bva: taken from https://lkml.org/lkml/2015/5/28/242]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/1 [
Author: "Chew, Chiau Ee"
Email: chiau.ee.chew@intel.com
Subject: spi/pxa2xx-pci: Add common clock framework support in PCI glue layer
Date: Fri, 25 Jul 2014 01:10:54 +0800
SPI PXA2XX core layer has dependency on common clock framework
to obtain information on host supported clock rate. Thus, we
setup the clock device in the PCI glue layer to enable PCI mode
host pass in the clock rate information.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Kweh, Hock Leong <hock.leong.kweh@intel.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/1 [
Author: Yang Shi
Email: yang.shi@windriver.com
Subject: vexpress: Pass LOADADDR to Makefile
Date: Tue, 15 Jul 2014 21:19:34 -0700
Due to upstream commit 938f94cde74b33d6d3580c6fe65ebe918a770ae2
("ARM: 7656/1: uImage: Error out on build of multiplatform without LOADADDR"),
vexpress BSP need LOADADDR for making uImage, so pass LOADADDR in the Makefile
for vexpress.
Signed-off-by: Yang Shi <yang.shi@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/24 [
Author: Thomas Gleixner
Email: tglx@linutronix.de
Subject: genirq: x86: Ensure that dynamic irq allocation does not conflict
Date: Thu, 24 Apr 2014 09:50:53 +0200
On x86 the allocation of irq descriptors may allocate interrupts which
are in the range of the GSI interrupts. That's wrong as those
interrupts are hardwired and we don't have the irq domain translation
like PPC. So one of these interrupts can be hooked up later to one of
the devices which are hard wired to it and the io_apic init code for
that particular interrupt line happily reuses that descriptor with a
completely different configuration so hell breaks lose.
Inside x86 we allocate dynamic interrupts from above nr_gsi_irqs,
except for a few usage sites which have not yet blown up in our face
for whatever reason. But for drivers which need an irq range, like the
GPIO drivers, we have no limit in place and we don't want to expose
such a detail to a driver.
To cure this introduce a function which an architecture can implement
to impose a lower bound on the dynamic interrupt allocations.
Implement it for x86 and set the lower bound to nr_gsi_irqs, which is
the end of the hardwired interrupt space, so all dynamic allocations
happen above.
That not only allows the GPIO driver to work sanely, it also protects
the bogus callsites of create_irq_nr() in hpet, uv, irq_remapping and
htirq code. They need to be cleaned up as well, but that's a separate
issue.
Reported-by: Jin Yao <yao.jin@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Mathias Nyman <mathias.nyman@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: H. Peter Anvin <hpa@linux.intel.com>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Krogerus Heikki <heikki.krogerus@intel.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Link: http://lkml.kernel.org/r/alpine.DEB.2.02.1404241617360.28206@ionos.tec.linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
(cherry picked from commit 62a08ae2a5763aabeee98264605236b001503e0c)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
2/24 [
Author: Mika Westerberg
Email: mika.westerberg@linux.intel.com
Subject: pwm: add support for Intel Low Power Subsystem PWM
Date: Thu, 20 Mar 2014 22:04:23 +0800
Add support for Intel Low Power I/O subsystem PWM controllers found on
Intel BayTrail SoC.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Chew, Kean Ho <kean.ho.chew@intel.com>
Signed-off-by: Chang, Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit d16a5aa9e821633a3095d7a88cd1d2cd108bf966)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
3/24 [
Author: "Chew, Chiau Ee"
Email: chiau.ee.chew@intel.com
Subject: ACPI / LPSS: Add Intel BayTrail ACPI mode PWM
Date: Wed, 19 Feb 2014 02:24:29 +0800
Intel BayTrail LPSS consists of two PWM controllers which can
be enumerated from ACPI namespace. This change will cause
platform device objects to be created for Intel BayTrail PWM
controllers which will allow the pwm-lpss driver to bind to them
and handle those devices.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
(cherry picked from commit e1c7481797542f4d2039d5a458ef80603298ad78)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
4/24 [
Author: Mika Westerberg
Email: mika.westerberg@linux.intel.com
Subject: i2c: designware-pci: Add Baytrail PCI IDs
Date: Wed, 19 Feb 2014 16:10:29 +0200
Intel Baytrail I2C controllers can be enumerated from PCI as well as from
ACPI. In order to support this add the Baytrail PCI IDs to the driver.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
(cherry picked from commit 089c729ae440c6df35eeac7998525718fcee0323)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
5/24 [
Author: Adrian Hunter
Email: adrian.hunter@intel.com
Subject: mmc: sdhci: Allow for irq being shared
Date: Tue, 11 Mar 2014 10:09:36 +0200
If the SDHCI irq is shared with another device then the interrupt
handler can get called while SDHCI is runtime suspended. That is
harmless but the warning message is not useful so remove it. Also
returning IRQ_NONE is more appropriate.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit 655bca7616bf6076d30b14d1478bca6807d49c45)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
6/24 [
Author: "Chew, Chiau Ee"
Email: chiau.ee.chew@intel.com
Subject: dma: dw: Add suspend and resume handling for PCI mode DW_DMAC.
Date: Sat, 15 Mar 2014 02:02:39 +0800
This is to disable/enable DW_DMAC hw during late suspend/early resume.
Since DMA is providing service to other clients (eg: SPI, HSUART),
we need to ensure DMA suspends after the clients and resume
before the clients are active.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
(cherry picked from commit 4501fe61b286e35be5b372a4f1ffcf5881ceeaed)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
7/24 [
Author: "Chew, Kean ho"
Email: kean.ho.chew@intel.com
Subject: i2c: i801: enable Intel BayTrail SMBUS
Date: Sat, 1 Mar 2014 00:03:56 +0800
Add Device ID of Intel BayTrail SMBus Controller.
Signed-off-by: Chew, Kean ho <kean.ho.chew@intel.com>
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
(cherry picked from commit 1b31e9b76ef8c62291e698dfdb973499986a7f68)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
8/24 [
Author: "Chew, Kean Ho"
Email: kean.ho.chew@intel.com
Subject: pinctrl-baytrail: add function mux checking in gpio pin request
Date: Thu, 6 Mar 2014 21:59:49 +0800
The requested gpio pin must has the func_pin_mux field set
to GPIO function by BIOS/FW in advanced. Else, the gpio pin
request would fail. This is to ensure that we do not expose
any gpio pins which shall be used for alternate functions,
for eg: wakeup pin, I/O interfaces for LPSS, etc.
Signed-off-by: Chew, Kean Ho <kean.ho.chew@intel.com>
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Reviewed-by: Darren Hart <dvhart@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 42bd00706ce95d74ad6ebcb8528ee1fbbb992f6a)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
9/24 [
Author: Paul Drews
Email: paul.drews@intel.com
Subject: ACPI: Add BayTrail SoC GPIO and LPSS ACPI IDs
Date: Mon, 25 Nov 2013 14:15:55 -0800
This adds the new ACPI ID (INT33FC) for the BayTrail GPIO
banks as seen on a BayTrail M System-On-Chip platform. This
ACPI ID is used by the BayTrail GPIO (pinctrl) driver to
manage the Low Power Subsystem (LPSS).
Signed-off-by: Paul Drews <paul.drews@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
(cherry picked from commit f6308b36c411dc5afd6a6f73e6454722bfde57b7)
This patch has been reverted in mainline, but the revert should not
longer be necessary with the x86 irq fix from Thomas Gleixner now in
mainline:
b6dae3b genirq: x86: Ensure that dynamic irq allocation does not conflict
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
10/24 [
Author: "Chew, Chiau Ee"
Email: chiau.ee.chew@intel.com
Subject: i2c: designware-pci: add 10-bit addressing mode functionality for BYT I2C
Date: Fri, 7 Mar 2014 22:12:50 +0800
All the I2C controllers on Intel BayTrail LPSS subsystem able
to support 10-bit addressing mode functionality.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Signed-off-by: Ong, Boon Leong <boon.leong.ong@intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
(cherry picked from commit ceccd298f6fd537457576017d604fc5aa6d3c82a)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
11/24 [
Author: Adrian Hunter
Email: adrian.hunter@intel.com
Subject: mmc: sdhci-acpi: Fix broken card detect for ACPI HID 80860F14
Date: Mon, 10 Mar 2014 15:02:42 +0200
Some 80860F14 devices do not support card detect and must rely
completely on GPIO. Presently the card detect GPIO is used
only to wake-up from runtime suspend. Change to using
mmc_gpioid_request_cd() which will cause the SDHCI driver to
prefer the GPIO to the host controller's native card detect.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit 4fd4409c81e2c756a5cfbedc598c48d6a3ed3fd5)
]
12/24 [
Author: Adrian Hunter
Email: adrian.hunter@intel.com
Subject: mmc: slot-gpio: Record GPIO descriptors instead of GPIO numbers
Date: Mon, 10 Mar 2014 15:02:39 +0200
In preparation for adding a descriptor-based CD GPIO API, switch from
recording GPIO numbers to recording GPIO descriptors.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit 842f4bdd37c7a0984e22aa919ad1f043137ac5c8)
]
13/24 [
Author: Adrian Hunter
Email: adrian.hunter@intel.com
Subject: mmc: slot-gpio: Split out CD IRQ request into a separate function
Date: Mon, 10 Mar 2014 15:02:40 +0200
In preparation for adding a descriptor-based CD GPIO API, split out
CD IRQ request into a separate function.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit 26652671338a443fd33cf47b50658dd8b095d54a)
]
14/24 [
Author: Adrian Hunter
Email: adrian.hunter@intel.com
Subject: mmc: slot-gpio: Add GPIO descriptor based CD GPIO API
Date: Mon, 10 Mar 2014 15:02:41 +0200
Add functions to request a CD GPIO using the GPIO descriptor API.
Note that the new request function is paired with mmc_gpiod_free_cd()
not mmc_gpio_free_cd(). Note also that it must be called prior to
mmc_add_host() otherwise the caller must also call
mmc_gpiod_request_cd_irq().
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit 740a221ef0e579dc7c675cf6b90f5313509788f7)
]
15/24 [
Author: Adrian Hunter
Email: adrian.hunter@intel.com
Subject: mmc: sdhci-acpi: Add device id 80860F16
Date: Mon, 10 Mar 2014 15:02:43 +0200
Add ACPI HID 80860F16 as a host controller for a SD card.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit aad95dc49c6dad19b49af7cd90c53473ec0536d1)
]
16/24 [
Author: "Chew, Chiau Ee"
Email: chiau.ee.chew@intel.com
Subject: i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value
Date: Tue, 11 Mar 2014 19:33:45 +0800
On Intel BayTrail, there was case whereby the resulting fast mode
bus speed becomes slower (~20% slower compared to expected speed)
if using the HCNT/LCNT calculated in the core layer. Thus, this
patch is added to allow pci glue layer to pass in optimal
HCNT/LCNT/SDA hold time values to core layer since the core
layer supports cofigurable HCNT/LCNT/SDA hold time values now.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
(cherry picked from commit 8efd1e9ee3bd55e20cb36e56ca53096cf2b3a930)
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
17/24 [
Author: Adrian Hunter
Email: adrian.hunter@intel.com
Subject: mmc: sdhci-acpi: Intel SDIO has broken card detect
Date: Thu, 3 Apr 2014 14:58:39 +0300
Intel SDIO has broken card detect so add a quirk to reflect that.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
(cherry picked from commit c67480173f72e883235dd0ad09d90156c8f87600)
]
18/24 [
Author: "Chew, Chiau Ee"
Email: chiau.ee.chew@intel.com
Subject: spi/pxa2xx-pci: Add PCI mode support for BayTrail LPSS SPI
Date: Fri, 18 Apr 2014 00:26:06 +0800
Similar to CE4100, BayTrail LPSS SPI can be PCI enumerated
as well. Thus, the functions are renamed from ce4100_xxx
to pxa2xx_spi_pci_xxx to clarify that this is a generic
PCI glue layer. Also, added required infrastructure to
support SPI hosts with different configurations.
This patch is based on Mika Westerberg's previous work.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit d6ba32d5c60f569d252ec9dcd96cd46b19785b60)
From linux-next
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
19/24 [
Author: Darren Hart
Email: dvhart@linux.intel.com
Subject: drm/i915/vlv: reset VLV media force wake request register
Date: Fri, 9 May 2014 08:43:09 -0700
Media force wake get hangs the machine when the system is booted without
displays attached. The assumption is that (at least some versions of)
the firmware has skipped some initialization in that case.
Empirical evidence suggests we need to reset the media force wake
request register in addition to the render one to avoid hangs.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75895
Reported-by: Imre Deak <imre.deak@intel.com>
Reported-by: Darren Hart <dvhart@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
]
20/24 [
Author: Alan Cox
Email: alan@linux.intel.com
Subject: pwm: lpss: Add support for PCI devices
Date: Fri, 18 Apr 2014 19:17:40 +0800
Not all systems enumerate the PWM devices via ACPI. They can also be
exposed via the PCI interface.
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit 093e00bb3f82f3c67e2d1682e316fc012bcd0d92)
From linux-next/next-20140512
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
21/24 [
Author: Thierry Reding
Email: thierry.reding@gmail.com
Subject: pwm: lpss: Fix const qualifier and sparse warnings
Date: Wed, 7 May 2014 10:27:57 +0200
Fixes the following warnings reported by the 0-DAY kernel build testing
backend:
drivers/pwm/pwm-lpss.c: In function 'pwm_lpss_probe_pci':
>> drivers/pwm/pwm-lpss.c:192:2: warning: passing argument 3 of 'pwm_lpss_probe' discards 'const' qualifier from pointer target type [enabled by default]
lpwm = pwm_lpss_probe(&pdev->dev, &pdev->resource[0], info);
^
drivers/pwm/pwm-lpss.c:130:30: note: expected 'struct pwm_lpss_boardinfo *' but argument is of type 'const struct pwm_lpss_boardinfo *'
static struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev,
^
>> drivers/pwm/pwm-lpss.c:143:28: sparse: incorrect type in return expression (different address spaces)
drivers/pwm/pwm-lpss.c:143:28: expected struct pwm_lpss_chip *
drivers/pwm/pwm-lpss.c:143:28: got void [noderef] <asn:2>*regs
>> drivers/pwm/pwm-lpss.c:192:63: sparse: incorrect type in argument 3 (different modifiers)
drivers/pwm/pwm-lpss.c:192:63: expected struct pwm_lpss_boardinfo *info
drivers/pwm/pwm-lpss.c:192:63: got struct pwm_lpss_boardinfo const *[assigned] info
drivers/pwm/pwm-lpss.c: In function 'pwm_lpss_probe_pci':
drivers/pwm/pwm-lpss.c:192:2: warning: passing argument 3 of 'pwm_lpss_probe' discards 'const' qualifier from pointer target type [enabled by default]
lpwm = pwm_lpss_probe(&pdev->dev, &pdev->resource[0], info);
^
drivers/pwm/pwm-lpss.c:130:30: note: expected 'struct pwm_lpss_boardinfo *' but argument is of type 'const struct pwm_lpss_boardinfo *'
static struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev,
^
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
(cherry picked from commit 89c0339e0aa097384b3efed894b23820814c21d3)
From linux-next/next-20140512
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
22/24 [
Author: Darren Hart
Email: dvhart@linux.intel.com
Subject: clkdev: Export clk_register_clkdev
Date: Fri, 9 May 2014 14:14:45 -0700
Allow spi-pxa2xx-pci with common clock framework support to build as a
module by exporting clk_register_clkdev.
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
Cc: "Chew, Chiau Ee" <chiau.ee.chew@intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
]
23/24 [
Author: "Chew, Chiau Ee"
Email: chiau.ee.chew@intel.com
Subject: spi/pxa2xx: Add common clock framework support in PCI glue layer
Date: Thu, 8 May 2014 15:36:11 -0700
SPI PXA2XX core layer has dependency on common clock framework
to obtain information on host supported clock rate. Thus, we
setup the clock device in the PCI glue layer to enable PCI mode
host pass in the clock rate information.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
PENDING: Out for review
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
24/24 [
Author: Darren Hart
Email: dvhart@linux.intel.com
Subject: acpi_lpss: Add Bay Trail pinctrl HID
Date: Mon, 28 Apr 2014 07:16:46 -0700
Add the newer Bay Trail pinctrl HID to the acpi_lpss acpi match table.
Without this, the pinctrl-baytrail.c driver doesn't match the device and
the GPIO are not visible.
PENDING: Out for review
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
|
|
1/1 [
Author: "Yang,Wei"
Email: Wei.Yang@windriver.com
Subject: MIPS: octeon: Fix warning in of_device_alloc on cn3xxx
Date: Thu, 20 Mar 2014 09:03:18 +0800
Starting with commit 3da5278727a895d49a601f67fd49dffa0b80f9a5 (of/irq:
Rework of_irq_count()) the following warning is triggered on octeon
cn3xxx:
[ 0.887281] WARNING: CPU: 0 PID: 1 at drivers/of/platform.c:171 of_device_alloc+0x228/0x230()
[ 0.895642] Modules linked in:
[ 0.898689] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.14.0-rc7-00012-g9ae51f2-dirty #41
[ 0.906860] Stack : c8b439581166d96e ffffffff816b0000 0000000040808000 ffffffff81185ddc
[ 0.906860] 0000000000000000 0000000000000000 0000000000000000 000000000000000b
[ 0.906860] 000000000000000a 000000000000000a 0000000000000000 0000000000000000
[ 0.906860] ffffffff81740000 ffffffff81720000 ffffffff81615900 ffffffff816b0177
[ 0.906860] ffffffff81727d10 800000041f868fb0 0000000000000001 0000000000000000
[ 0.906860] 0000000000000000 0000000000000038 0000000000000001 ffffffff81568484
[ 0.906860] 800000041f86faa8 ffffffff81145ddc 0000000000000000 ffffffff811873f4
[ 0.906860] 800000041f868b88 800000041f86f9c0 0000000000000000 ffffffff81569c9c
[ 0.906860] 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[ 0.906860] 0000000000000000 ffffffff811205e0 0000000000000000 0000000000000000
[ 0.906860] ...
[ 0.971695] Call Trace:
[ 0.974139] [<ffffffff811205e0>] show_stack+0x68/0x80
[ 0.979183] [<ffffffff81569c9c>] dump_stack+0x8c/0xe0
[ 0.984196] [<ffffffff81145efc>] warn_slowpath_common+0x84/0xb8
[ 0.990110] [<ffffffff81436888>] of_device_alloc+0x228/0x230
[ 0.995726] [<ffffffff814368d8>] of_platform_device_create_pdata+0x48/0xd0
[ 1.002593] [<ffffffff81436a94>] of_platform_bus_create+0x134/0x1e8
[ 1.008837] [<ffffffff81436af8>] of_platform_bus_create+0x198/0x1e8
[ 1.015064] [<ffffffff81436cc4>] of_platform_bus_probe+0xa4/0x100
[ 1.021149] [<ffffffff81100570>] do_one_initcall+0xd8/0x128
[ 1.026701] [<ffffffff816e2a10>] kernel_init_freeable+0x144/0x210
[ 1.032753] [<ffffffff81564bc4>] kernel_init+0x14/0x110
[ 1.037973] [<ffffffff8111bb44>] ret_from_kernel_thread+0x14/0x1c
With this commit the kernel starts mapping the interrupts listed for
gpio-controller node. irq_domain_ops for CIU (octeon_irq_ciu_map and
octeon_irq_ciu_xlat) refuse to handle the GPIO lines (returning -EINVAL)
and this is causing above warning in of_device_alloc().
Modify irq_domain_ops for CIU and CIU2 to "gracefully handle" GPIO
lines (neither return error code nor call octeon_irq_set_ciu_mapping
for it). This should avoid the warning.
(As before the real setup for GPIO lines will happen using
irq_domain_ops of gpio-controller.)
This patch is based on Wei's patch v2 (see
http://marc.info/?l=linux-mips&m=139511814813247).
Reported-by: Yang Wei <wei.yang@windriver.com>
Cc: David Daney <david.daney@caviumnetworks.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
|
|
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
|
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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optimizations
1/2 [
Author: Ivan Djelic
Email: ivan.djelic@parrot.com
Subject: ARM: 7668/1: fix memset-related crashes caused by recent GCC (4.7.2) optimizations
Date: Wed, 6 Mar 2013 20:09:27 +0100
Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on
assumptions about the implementation of memset and similar functions.
The current ARM optimized memset code does not return the value of
its first argument, as is usually expected from standard implementations.
For instance in the following function:
void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter)
{
memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter));
waiter->magic = waiter;
INIT_LIST_HEAD(&waiter->list);
}
compiled as:
800554d0 <debug_mutex_lock_common>:
800554d0: e92d4008 push {r3, lr}
800554d4: e1a00001 mov r0, r1
800554d8: e3a02010 mov r2, #16 ; 0x10
800554dc: e3a01011 mov r1, #17 ; 0x11
800554e0: eb04426e bl 80165ea0 <memset>
800554e4: e1a03000 mov r3, r0
800554e8: e583000c str r0, [r3, #12]
800554ec: e5830000 str r0, [r3]
800554f0: e5830004 str r0, [r3, #4]
800554f4: e8bd8008 pop {r3, pc}
GCC assumes memset returns the value of pointer 'waiter' in register r0; causing
register/memory corruptions.
This patch fixes the return value of the assembly version of memset.
It adds a 'mov' instruction and merges an additional load+store into
existing load/store instructions.
For ease of review, here is a breakdown of the patch into 4 simple steps:
Step 1
======
Perform the following substitutions:
ip -> r8, then
r0 -> ip,
and insert 'mov ip, r0' as the first statement of the function.
At this point, we have a memset() implementation returning the proper result,
but corrupting r8 on some paths (the ones that were using ip).
Step 2
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 1:
save r8:
- str lr, [sp, #-4]!
+ stmfd sp!, {r8, lr}
and restore r8 on both exit paths:
- ldmeqfd sp!, {pc} @ Now <64 bytes to go.
+ ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go.
(...)
tst r2, #16
stmneia ip!, {r1, r3, r8, lr}
- ldr lr, [sp], #4
+ ldmfd sp!, {r8, lr}
Step 3
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 0:
save r8:
- stmfd sp!, {r4-r7, lr}
+ stmfd sp!, {r4-r8, lr}
and restore r8 on both exit paths:
bgt 3b
- ldmeqfd sp!, {r4-r7, pc}
+ ldmeqfd sp!, {r4-r8, pc}
(...)
tst r2, #16
stmneia ip!, {r4-r7}
- ldmfd sp!, {r4-r7, lr}
+ ldmfd sp!, {r4-r8, lr}
Step 4
======
Rewrite register list "r4-r7, r8" as "r4-r8".
Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
]
2/2 [
Author: Nicolas Pitre
Email: nicolas.pitre@linaro.org
Subject: ARM: 7670/1: fix the memset fix
Date: Tue, 12 Mar 2013 13:00:42 +0100
Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
with the memset return value. However the memset itself became broken
by that patch for misaligned pointers.
This fixes the above by branching over the entry code from the
misaligned fixup code to avoid reloading the original pointer.
Also, because the function entry alignment is wrong in the Thumb mode
compilation, that fixup code is moved to the end.
While at it, the entry instructions are slightly reworked to help dual
issue pipelines.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Alexander Holler <holler@ahsoftware.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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|
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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|
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/2 [
Author: Ben Hutchings
Email: ben@decadent.org.uk
Subject: signal: Define __ARCH_HAS_SA_RESTORER so we know whether to clear sa_restorer
Date: Sun, 25 Nov 2012 22:24:19 -0500
flush_signal_handlers() needs to know whether sigaction::sa_restorer
is defined, not whether SA_RESTORER is defined. Define the
__ARCH_HAS_SA_RESTORER macro to indicate this.
Vaguely based on upstream commit 574c4866e33d 'consolidate kernel-side
struct sigaction declarations'.
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Cc: Al Viro <viro@zeniv.linux.org.uk>
]
2/2 [
Author: Andrew Morton
Email: akpm@linux-foundation.org
Subject: kernel/signal.c: use __ARCH_HAS_SA_RESTORER instead of SA_RESTORER
Date: Wed, 13 Mar 2013 14:59:34 -0700
__ARCH_HAS_SA_RESTORER is the preferred conditional for use in 3.9 and
later kernels, per Kees.
Cc: Emese Revfy <re.emese@gmail.com>
Cc: Emese Revfy <re.emese@gmail.com>
Cc: PaX Team <pageexec@freemail.hu>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: "Eric W. Biederman" <ebiederm@xmission.com>
Cc: Serge Hallyn <serge.hallyn@canonical.com>
Cc: Julien Tinnes <jln@google.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/1 [
Author: Bruce Ashfield
Email: bruce.ashfield@windriver.com
Subject: mips: fix signal.h SA_RESTORER build breakage
Date: Mon, 25 Mar 2013 12:28:06 -0700
-stable commit cdef9602 [signal: always clear sa_restorer on execve]
assumes the presence of sa_restorer in the signal_handler structure.
This is not the case for MIPS o32, although the architecture does
defined SA_RESTORER. To fix this, we add the structure to the mips
local copy of signal.h.
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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|
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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This seems like a logical grouping to reduce the cluster
accumulation in cfg for another while.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Most of the in tree kernel.org MIPS defconfigs call out a HZ
value of 100, so align our choice with that value.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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None of the in tree kernel.org ARM defconfigs call out a HZ
value, so they get the Kconfig default value. Align our
choice with that value.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Seen while rummaging around looking for v7/A15 content.
These could probably be nominated for v3.4.x stable and
then dropped from here. Queue them here 1st to see if they
actually cause unexpected fallout somewhere.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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|
Commits selected here for ARMv7/A15; based on the rough ordering of
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
but by choosing mainline versions thereof when they exist.
commit e423c0c30c76fc850a443102a2965ec397ba6e21
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Merge branch 'intr-ctxsw' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux into devel-stable
ARM-Use-TTBR1-instead-of-reserved-context-ID.patch
ARM-Remove-__ARCH_WANT_INTERRUPTS_ON_CTXSW-on-ASID-c.patch
ARM-Remove-current_mm-per-cpu-variable.patch
ARM-Remove-__ARCH_WANT_INTERRUPTS_ON_CTXSW-on-pre-AR.patch
commit 5693188a6e888603afa9564974145e5e6e2c623c
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Merge branch 'timers-v3.4-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into devel-stable
ARM-local-timers-reserve-local_timer_register-to-SMP.patch
ARM-local-timers-Add-A15-architected-timer-support.patch
ARM-architected-timers-Add-A15-specific-sched_clock-.patch
ARM-architected-timers-add-DT-support.patch
ARM-architected-timers-add-support-for-UP-timer.patch
ARM-vexpress-plug-local-timers-into-the-DT-code.patch
ARM-architected-timers-remove-support-for-non-DT-pla.patch
This one is in maz tree but not mainlined for v3.5 yet.
ARM-LPAE-Invalidate-the-TLB-for-module-addresses-dur.patch
A lot of the LPAE specific commits actually got mainlined in v3.4 (yay).
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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.irq_mask is set twice in:
arch/mips/sibyte/sb1250/irq.c:
static struct irq_chip sb1250_irq_type = {
.name = "SB1250-IMR",
.irq_mask = ack_sb1250_irq,
.irq_unmask = enable_sb1250_irq,
.irq_mask = disable_sb1250_irq,
".irq_mask = ack_sb1250_irq" comes from
"arch/mips/mips-sibyte-Add-missing-irq_mask-function.patch"
While ".irq_mask = disable_sb1250_irq" comes from upstream:
1544129 MIPS: SB1250: Restore dropped irq_mask function
---
That being said:
disable_sb1250_irq() does just this:
sb1250_mask_irq(sb1250_irq_owner[irq], irq);
while ack_sb1250_irq() does a whole bunch of stuff and then at the end
it does the same thing as disable_sb1250_irq():
sb1250_mask_irq(sb1250_irq_owner[irq], irq);
To fix this we drop the whole patch and let the mainline default
do its thing.
Signed-off-by: Michel Thebeau <michel.thebeau@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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The following patches are no longer needed in the context of
a 3.4 kernel, or need to be refreshed:
arch/mips/mips.scc:16:patch MIPS-ARC-Fix-build-of-firmware-library-on.patch
ktypes/standard/standard-nocfg.scc:78:patch serial-PL011-move-interrupt-clearing.patch
patches/build/build.scc:4:patch kbuild-add-meta-files-to-the-ignore-li.patch
arch/mips/mips.scc:8:patch mips-sibyte-Add-missing-irq_mask-function.patch
arch/mips/mips-support-preemptible-kernel.patch
features/uptime/uptime-allow-the-optional-limiting-of-kernel-runtime.patch
ktypes/standard/perf-force-include-of-stdbool.h.patch
patches/boot/nfs-Allow-default-io-size-to-be-configured.patch
Signed-off-by: Michel Thebeau <michel.thebeau@windriver.com>
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
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|
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/1 [
Author: Darren Hart
Email: dvhart@linux.intel.com
Subject: MIPS: ARC: Fix build of firmware library on
Date: Thu, 11 Aug 2011 00:25:53 -0700
commit 4f55fd752fb4770a354dd2401d5043c98236cc29 upstream
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[applied to linux-yocto standard/base]
Signed-off-by: Darren Hart <dvhart@linux.intel.com>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/7 [
Author: Thomas Gleixner
Email: tglx@linutronix.de
Subject: mips: sibyte: Add missing irq_mask function
Date: Sat, 23 Jul 2011 11:41:22 +0000
Crashes on free_irq() otherwise.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
]
2/7 [
Author: Thomas Gleixner
Email: tglx@linutronix.de
Subject: mips: ftrace: Fix the CONFIG_DYNAMIC_FTRACE=n compile
Date: Sat, 23 Jul 2011 11:41:23 +0000
arch/mips/kernel/ftrace.c: In function ‘ftrace_get_parent_ra_addr’:
arch/mips/kernel/ftrace.c:212: error: implicit declaration of function ‘in_kernel_space’
arch/mips/kernel/ftrace.c: In function ‘prepare_ftrace_return’:
arch/mips/kernel/ftrace.c:314: error: ‘MCOUNT_OFFSET_INSNS’ undeclared (first use in this function)
arch/mips/kernel/ftrace.c:314: error: (Each undeclared identifier is reported only once
arch/mips/kernel/ftrace.c:314: error: for each function it appears in.)
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
]
3/7 [
Author: Thomas Gleixner
Email: tglx@linutronix.de
Subject: mips: Enable interrupts in do_signal()
Date: Sat, 23 Jul 2011 11:41:23 +0000
do_signal() does __put_user() which can fault, resulting in a
might_sleep() warning in down_read(&mm->mmap_sem) and a "scheduling
while atomic" warning when mmap_sem is contented. On swarm this also
results in:
WARNING: at kernel/smp.c:459 smp_call_function_many+0x148/0x398()
Modules linked in:
Call Trace:
[<ffffffff804b48a4>] dump_stack+0x1c/0x50
[<ffffffff8013dc94>] warn_slowpath_common+0x8c/0xc8
[<ffffffff8013dcfc>] warn_slowpath_null+0x2c/0x40
[<ffffffff801864a0>] smp_call_function_many+0x148/0x398
[<ffffffff80186748>] smp_call_function+0x58/0xa8
[<ffffffff80119b5c>] r4k_flush_data_cache_page+0x54/0xd8
[<ffffffff801f39bc>] handle_pte_fault+0xa9c/0xad0
[<ffffffff801f40d0>] handle_mm_fault+0x158/0x200
[<ffffffff80115548>] do_page_fault+0x218/0x3b0
[<ffffffff80102744>] ret_from_exception+0x0/0x10
[<ffffffff8010eb18>] copy_siginfo_to_user32+0x50/0x298
[<ffffffff8010edf0>] setup_rt_frame_32+0x90/0x250
[<ffffffff80106414>] do_notify_resume+0x154/0x358
[<ffffffff80102930>] work_notifysig+0xc/0x14
Enable interrupts in do_signal() before delivering signals. Might be
done in the entry code before calling do_notify_resume(), but I leave
that for the MIPS ASM wizards.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
]
4/7 [
Author: Wu Zhangjin
Email: wuzhangjin@gmail.com
Subject: MIPS: Make the die_lock be raw
Date: Sat, 23 Jul 2011 11:41:24 +0000
On preempt-rt this lock needs to be raw, so it does not get converted
to a sleeping spinlock. Trying to sleep in a panic is not really
desireable.
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
]
5/7 [
Author: Wu Zhangjin
Email: wuzhangjin@gmail.com
Subject: MIPS: Mark cascade and low level interrupts IRQF_NO_THREAD
Date: Sat, 23 Jul 2011 11:41:24 +0000
Mark interrupts with no_action handler, cascade interrupts, low level
interrupts (bus error, halt ..) with IRQF_NO_THREAD to exclude them
from forced threading.
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
]
6/7 [
Author: Wu Zhangjin
Email: wuzhangjin@gmail.com
Subject: MIPS: Loongson: Mark cascade interrupts IRQF_NO_THREAD
Date: Sat, 23 Jul 2011 11:41:24 +0000
There are two cascade interrupts in Loongson machines, one for bonito
northbridge, another for the 8259A controller in the southbridge. Both
want to be non threaded.
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
]
7/7 [
Author: Thomas Gleixner
Email: tglx@linutronix.de
Subject: mips: Allow forced irq threading
Date: Sat, 23 Jul 2011 11:41:25 +0000
All low level interrupts have been marked NO_THREAD, so MIPS can enjoy
the wonderful world of forced threaded interrupt handlers.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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1/2 [
Author: David Daney
Email: david.daney@cavium.com
Subject: MIPS: Add uasm UASM_i_SRL_SAFE macro.
Date: Tue, 5 Jul 2011 16:34:45 -0700
commit 52b4746d272298523d58d4ca2bc92013189ac728 in git://git.linux-mips.org/pub/scm/linux
This can be used from either 32-bit or 64-bit code to generate logical
right shifts of any constant amount.
Signed-off-by: David Daney <david.daney@cavium.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2576/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
(cherry picked from commit e4593fafd508564aae1135f2b17574f6f012695f)
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2/2 [
Author: David Daney
Email: david.daney@cavium.com
Subject: MIPS: Close races in TLB modify handlers.
Date: Tue, 5 Jul 2011 16:34:46 -0700
commit 2205d3c9364a10b4151949ced5a9bcc08e9ff38b in git://git.linux-mips.org/pub/scm/linux
Page table entries are made invalid by writing a zero into the the PTE
slot in a page table. This creates a race condition with the TLB
modify handlers when they are updating the PTE.
CPU0 CPU1
Test for _PAGE_PRESENT
. set to not _PAGE_PRESENT (zero)
Set to _PAGE_VALID
So now the page not present value (zero) is suddenly valid and user
space programs have access to physical page zero.
We close the race by putting the test for _PAGE_PRESENT and setting of
_PAGE_VALID into an atomic LL/SC section. This requires more registers
than just K0 and K1 in the handlers, so we need to save some registers
to a save area and then restore them when we are done.
The save area is an array of cacheline aligned structures that should
not suffer cache line bouncing as they are CPU private.
[ralf@linux-mips.org: Fix !defined(CONFIG_MIPS_PGD_C0_CONTEXT) build error.]
Signed-off-by: David Daney <david.daney@cavium.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2577/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
(cherry picked from commit 7211f4d7a3dcbe57c5d396c334dca525315dceb2)
]
Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
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Paul Gortmaker
Bruce Ashfield
Michel Thebeau