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From 8c6891009d48c0c8b3f9aa98a50e3fe695df58b9 Mon Sep 17 00:00:00 2001
From: Le Ma <le.ma@amd.com>
Date: Wed, 7 Aug 2019 15:17:38 +0800
Subject: [PATCH 3323/4256] drm/amdgpu: enable hdp clock gating for Arcturus
Init hdp MGCG/LS flag as Vega20
Change-Id: Ia33ca064f79ac409c53d3beb6f01b6e814a92041
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 162f9c1d7c8f..ccc040c14399 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -1121,7 +1121,9 @@ static int soc15_common_early_init(void *handle)
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS |
AMD_CG_SUPPORT_GFX_CGCG |
- AMD_CG_SUPPORT_GFX_CGLS;
+ AMD_CG_SUPPORT_GFX_CGLS |
+ AMD_CG_SUPPORT_HDP_MGCG |
+ AMD_CG_SUPPORT_HDP_LS;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x32;
break;
--
2.17.1
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