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From 910bb3b65f4b3f4dd2f870ea86fcab335a84eda5 Mon Sep 17 00:00:00 2001
From: Tao Zhou <tao.zhou1@amd.com>
Date: Mon, 29 Jul 2019 14:50:35 +0800
Subject: [PATCH 3248/4256] drm/amdgpu: add macro of umc for each channel
common function for all umc versions, loop for each umc channel is
a frequent used operation in umc block, define it as a macro to
simplify code
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
index 2604f5076867..9efdd66279e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
@@ -21,6 +21,29 @@
#ifndef __AMDGPU_UMC_H__
#define __AMDGPU_UMC_H__
+/*
+ * void (*func)(struct amdgpu_device *adev, struct ras_err_data *err_data,
+ * uint32_t umc_reg_offset, uint32_t channel_index)
+ */
+#define amdgpu_umc_for_each_channel(func) \
+ struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; \
+ uint32_t umc_inst, channel_inst, umc_reg_offset, channel_index; \
+ for (umc_inst = 0; umc_inst < adev->umc.umc_inst_num; umc_inst++) { \
+ /* enable the index mode to query eror count per channel */ \
+ adev->umc.funcs->enable_umc_index_mode(adev, umc_inst); \
+ for (channel_inst = 0; \
+ channel_inst < adev->umc.channel_inst_num; \
+ channel_inst++) { \
+ /* calc the register offset according to channel instance */ \
+ umc_reg_offset = adev->umc.channel_offs * channel_inst; \
+ /* get channel index of interleaved memory */ \
+ channel_index = adev->umc.channel_idx_tbl[ \
+ umc_inst * adev->umc.channel_inst_num + channel_inst]; \
+ (func)(adev, err_data, umc_reg_offset, channel_index); \
+ } \
+ } \
+ adev->umc.funcs->disable_umc_index_mode(adev);
+
struct amdgpu_umc_funcs {
void (*ras_init)(struct amdgpu_device *adev);
void (*query_ras_error_count)(struct amdgpu_device *adev,
--
2.17.1
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