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From 28b87c242ab012fe790a12360762d90844a294ab Mon Sep 17 00:00:00 2001
From: Kevin Wang <kevin1.wang@amd.com>
Date: Fri, 12 Jul 2019 14:40:12 +0800
Subject: [PATCH 2865/2940] drm/amd/powerplay: add socclk profile dpm support.
1.miss socclk profile support when bringup.
2.add feature check for socclk.
Change-Id: I8ffef4c2e5760ba626bdce6b14e3be82e9b38e38
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 67db2746ec4f..5b64eea4303a 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -149,6 +149,11 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
pr_warn("gfxclk dpm is not enabled\n");
return 0;
}
+ case SMU_SOCCLK:
+ if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+ pr_warn("sockclk dpm is not enabled\n");
+ return 0;
+ }
break;
default:
break;
@@ -1389,6 +1394,7 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu,
return ret;
smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
+ smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
break;
case AMD_DPM_FORCED_LEVEL_MANUAL:
--
2.17.1
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