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From b1922c69c8eaab545c27f0c6e0935f3c223c7556 Mon Sep 17 00:00:00 2001
From: Kevin Wang <kevin1.wang@amd.com>
Date: Mon, 17 Jun 2019 13:05:00 +0800
Subject: [PATCH 2592/2940] drm/amd/powerplay: add feature check in
unforce_dpm_levels function
if not check dpm feature is enabled, it will cause show smc send message
failed log in dmesg log.
eg:
echo "auto" > power_dpm_force_performance_level
Change-Id: Iacc1b08fd35b5c75fa573ddace7a481efe9341f7
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rui Teng <rui.teng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 22d6a5cf3857..66fb2ee7331b 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -815,14 +815,21 @@ static int navi10_unforce_dpm_levels(struct smu_context *smu) {
uint32_t min_freq, max_freq;
enum smu_clk_type clk_type;
- enum smu_clk_type clks[] = {
- SMU_GFXCLK,
- SMU_MCLK,
- SMU_SOCCLK,
+ struct clk_feature_map {
+ enum smu_clk_type clk_type;
+ uint32_t feature;
+ } clk_feature_map[] = {
+ {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
+ {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT},
+ {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
};
- for (i = 0; i < ARRAY_SIZE(clks); i++) {
- clk_type = clks[i];
+ for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
+ if (!smu_feature_is_enabled(smu, clk_feature_map[i].feature))
+ continue;
+
+ clk_type = clk_feature_map[i].clk_type;
+
ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
if (ret)
return ret;
--
2.17.1
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