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From 9b441f76beff3977f9e9ae55515cd9674b672e54 Mon Sep 17 00:00:00 2001
From: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Date: Thu, 28 Mar 2019 14:43:29 -0400
Subject: [PATCH 2494/2940] drm/amd/display: Fix DCFCLK and SOCCLK not set
[Why]
If voltage level > 0, DCFCLK and SOCCLK could be 0 during DML
calculations, which ended up causing an assert.
[How]
Initialize dcfclk_mhz and socclk_mhz values according to the
voltage level.
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index aa04df64522f..dc3aa7debad5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2136,6 +2136,10 @@ bool dcn20_validate_bandwidth(struct dc *dc,
if (pipe_cnt != pipe_idx)
pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, &context->res_ctx, pipes);
+ pipes[0].clks_cfg.voltage = vlevel;
+ pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
+ pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
+
/* only pipe 0 is read for voltage and dcf/soc clocks */
if (vlevel < 1) {
pipes[0].clks_cfg.voltage = 1;
--
2.17.1
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