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From 345b074bc4ad96e6215d90a622fb617ab8d3ce61 Mon Sep 17 00:00:00 2001
From: Jack Xiao <Jack.Xiao@amd.com>
Date: Mon, 6 May 2019 16:35:41 +0800
Subject: [PATCH 2338/2940] drm/amdgpu: RLC must be disabled after SMU when S3
on navi
SMU requires to interact with RLC when disable all features,
so RLC shouldn't be disabled ahead of SMU.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 +---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 716467388c2d..262c4004939f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1596,8 +1596,6 @@ void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
-
- gfx_v10_0_enable_gui_idle_interrupt(adev, false);
}
static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
@@ -3630,7 +3628,7 @@ static int gfx_v10_0_hw_fini(void *handle)
return 0;
}
gfx_v10_0_cp_enable(adev, false);
- gfx_v10_0_rlc_stop(adev);
+ gfx_v10_0_enable_gui_idle_interrupt(adev, false);
return 0;
}
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 652963e52a5a..21a47d08d703 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -943,6 +943,10 @@ static int smu_suspend(void *handle)
smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
+ if (adev->asic_type >= CHIP_NAVI10 &&
+ adev->gfx.rlc.funcs->stop)
+ adev->gfx.rlc.funcs->stop(adev);
+
return 0;
}
--
2.17.1
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