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From 78496aae3a1bdd699182f5bd162dadfa81140856 Mon Sep 17 00:00:00 2001
From: Hawking Zhang <Hawking.Zhang@amd.com>
Date: Tue, 31 Jul 2018 15:00:40 +0800
Subject: [PATCH 2172/2940] drm/amdgpu: add module parameter for async_gfx_ring
enablement
0 means disable async_gfx_ring and is the default setting
1 means enable async_gfx_ring
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jack Xiao <jack.xiao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 ++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.rej | 25 ---------------------
3 files changed, 10 insertions(+), 25 deletions(-)
delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.rej
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c39153c2869a..cc51bbe212e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -161,6 +161,7 @@ extern uint amdgpu_dm_abm_level;
extern struct amdgpu_mgpu_info mgpu_info;
extern int amdgpu_ras_enable;
extern uint amdgpu_ras_mask;
+extern int amdgpu_async_gfx_ring;
#ifdef CONFIG_DRM_AMDGPU_SI
extern int amdgpu_si_support;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 7e34e9701d9e..eee755f46186 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -141,6 +141,7 @@ int amdgpu_emu_mode = 0;
uint amdgpu_smu_memory_pool_size = 0;
/* FBC (bit 0) disabled by default*/
uint amdgpu_dc_feature_mask = 0;
+int amdgpu_async_gfx_ring = 0;
struct amdgpu_mgpu_info mgpu_info = {
.mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
@@ -577,6 +578,14 @@ MODULE_PARM_DESC(smu_memory_pool_size,
"0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
+/**
+ * DOC: async_gfx_ring (int)
+ * It is used to enable gfx rings that could be configured with different prioritites or equal priorities
+ */
+MODULE_PARM_DESC(async_gfx_ring,
+ "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled (default), 1 = enabled)");
+module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
+
/**
* DOC: dcfeaturemask (uint)
* Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.rej b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.rej
deleted file mode 100644
index 45e382c74eee..000000000000
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c.rej
+++ /dev/null
@@ -1,25 +0,0 @@
---- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-+++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
-@@ -511,6 +513,22 @@ module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
- MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
- module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
-
-+/*
-+ * DOC: amdgpu_ras_enable (int)
-+ * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))
-+ */
-+MODULE_PARM_DESC(amdgpu_ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
-+module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
-+
-+/**
-+ * DOC: amdgpu_ras_mask (uint)
-+ * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1
-+ * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
-+ */
-+MODULE_PARM_DESC(amdgpu_ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
-+module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
-+
-+
- /**
- * DOC: si_support (int)
- * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled,
--
2.17.1
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