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From 3d4d5247620067b8304c2a5c1ece7c186acc873a Mon Sep 17 00:00:00 2001
From: James Zhu <James.Zhu@amd.com>
Date: Wed, 8 May 2019 16:38:58 -0400
Subject: [PATCH 1928/2940] drm/amdgpu: Fix S3 test issue
During S3 test, when system wake up and resume, ras interface
is already allocated. Move workaround before ras jumps to resume
step in gfx_v9_0_ecc_late_init, and make sure workaround applied
during resume. Also remove unused mmGB_EDC_MODE clearing.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 +++++---------
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 354d0feb545a..09b82ee99342 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3636,7 +3636,6 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
struct amdgpu_ib ib;
struct dma_fence *f = NULL;
int r, i, j;
- u32 tmp;
unsigned total_size, vgpr_offset, sgpr_offset;
u64 gpu_addr;
@@ -3648,9 +3647,6 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
if (!ring->sched.ready)
return 0;
- tmp = RREG32_SOC15(GC, 0, mmGB_EDC_MODE);
- WREG32_SOC15(GC, 0, mmGB_EDC_MODE, 0);
-
total_size =
((ARRAY_SIZE(vgpr_init_regs) * 3) + 4 + 5 + 2) * 4;
total_size +=
@@ -3816,6 +3812,11 @@ static int gfx_v9_0_ecc_late_init(void *handle)
return 0;
}
+ /* requires IBs so do in late init after IB pool is initialized */
+ r = gfx_v9_0_do_edc_gpr_workarounds(adev);
+ if (r)
+ return r;
+
if (*ras_if)
goto resume;
@@ -3823,11 +3824,6 @@ static int gfx_v9_0_ecc_late_init(void *handle)
if (!*ras_if)
return -ENOMEM;
- /* requires IBs so do in late init after IB pool is initialized */
- r = gfx_v9_0_do_edc_gpr_workarounds(adev);
- if (r)
- return r;
-
**ras_if = ras_block;
r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
--
2.17.1
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