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From 6023d98aa885fcf3eb0755c018b151596b4713d2 Mon Sep 17 00:00:00 2001
From: Yongqiang Sun <yongqiang.sun@amd.com>
Date: Thu, 3 Jan 2019 10:33:48 -0500
Subject: [PATCH 1527/2940] drm/amd/display: Access one register via dmub
offload.
Change-Id: Idb34b13b7f427b4638dfaf53b5deff067bb518b5
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index 0345d51e9d6f..c3e32051085b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -419,11 +419,19 @@ static bool optc1_enable_crtc(struct timing_generator *optc)
REG_UPDATE(CONTROL,
VTG0_ENABLE, 1);
+#ifdef CONFIG_DRM_AMD_DC_DMUB
+ REG_SEQ_START();
+#endif
/* Enable CRTC */
REG_UPDATE_2(OTG_CONTROL,
OTG_DISABLE_POINT_CNTL, 3,
OTG_MASTER_EN, 1);
+#ifdef CONFIG_DRM_AMD_DC_DMUB
+ REG_SEQ_SUBMIT();
+ REG_SEQ_WAIT_DONE();
+#endif
+
return true;
}
--
2.17.1
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