1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
|
From 3139dac5c1a699b980bcf5b2c8b0f41d1c09b191 Mon Sep 17 00:00:00 2001
From: Yongqiang Sun <yongqiang.sun@amd.com>
Date: Thu, 3 Jan 2019 11:49:47 -0500
Subject: [PATCH 1525/2940] drm/amd/display: Added register access processing.
Change-Id: I2378591facfbd0850ae0fb3a50cdc851162910e9
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../display/dmub_fw/src/common/dmub_common.h | 16 +++--
.../amd/display/dmub_fw/src/common/parser.c | 65 +++++++++++++++++++
2 files changed, 74 insertions(+), 7 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dmub_fw/src/common/parser.c
diff --git a/drivers/gpu/drm/amd/display/dmub_fw/src/common/dmub_common.h b/drivers/gpu/drm/amd/display/dmub_fw/src/common/dmub_common.h
index 5804de88346c..b7aa38890a7b 100644
--- a/drivers/gpu/drm/amd/display/dmub_fw/src/common/dmub_common.h
+++ b/drivers/gpu/drm/amd/display/dmub_fw/src/common/dmub_common.h
@@ -32,21 +32,23 @@ extern "C" {
#ifdef CONFIG_DRM_AMD_DC_DMUB
struct dmub_dc_cmd;
-struct dmub_inst {
+struct dmub {
void *ctx;
- void (*reg_write)(struct dmub_inst *inst, uint32_t offset, uint32_t value);
- uint32_t (*reg_read)(struct dmub_inst *inst, uint32_t offset);
+ void (*reg_write)(struct dmub *dmub, uint32_t offset, uint32_t value);
+ uint32_t (*reg_read)(struct dmub *dmub, uint32_t offset);
void (*dequeque)();
};
-extern const struct dc_context *g_ctx;
-
#define mmRegWrite(offset, value)
#define mmRegRead(offset)
#endif
-void process_ring_buffer_command(struct dmub_dc_cmd *dc_cmd);
-void ring_buffer_command_dequeue(struct dmub_dc_cmd *dmub_cmd, union dmub_rb_cmd *cmd);
+void process_ring_buffer_command(
+ struct dmub *dmub,
+ struct dmub_dc_cmd *dc_cmd);
+void ring_buffer_command_dequeue(
+ struct dmub_dc_cmd *dmub_cmd,
+ union dmub_rb_cmd *cmd);
#ifdef __cplusplus
}
diff --git a/drivers/gpu/drm/amd/display/dmub_fw/src/common/parser.c b/drivers/gpu/drm/amd/display/dmub_fw/src/common/parser.c
new file mode 100644
index 000000000000..fdbe40857310
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dmub_fw/src/common/parser.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#include "dmub_dc.h"
+#include "..\..\dc\dmub_cmd.h"
+#include "dmub_common.h"
+
+static void read_modify_write(struct dmub *dmub, union dmub_rb_cmd *cmd)
+{
+ int32_t reg_count =
+ cmd->read_modify_write.header.payload_bytes / sizeof(struct read_modify_write_sequence);
+ int32_t i;
+
+ for (i = 0; i < reg_count; i++) {
+ uint32_t addr = cmd->read_modify_write.seq[i].addr;
+ uint32_t mask = cmd->read_modify_write.seq[i].modify_mask;
+ uint32_t value = cmd->read_modify_write.seq[i].modify_value;
+ uint32_t reg_val = dmub->reg_read(dmub, addr);
+
+ reg_val = (reg_val & ~mask) | value;
+
+ dmub->reg_write(dmub, addr, reg_val);
+ }
+}
+
+void process_ring_buffer_command(
+ struct dmub *dmub,
+ struct dmub_dc_cmd *dc_cmd)
+{
+ union dmub_rb_cmd cmd;
+
+ ring_buffer_command_dequeue(dc_cmd, &cmd);
+
+ switch (cmd.cmd_common.header.type) {
+ case DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE:
+ read_modify_write(dmub, &cmd);
+ break;
+ case DMUB_CMD__REG_SEQ_BURST_WRITE:
+ break;
+ default:
+ break;
+ }
+}
+
--
2.17.1
|
