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From daa61047cc1f755d3de599ded4d70c17bfdefc74 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
Date: Mon, 16 Jul 2018 14:59:26 +0200
Subject: [PATCH 0103/2940] drm/amdgpu: use scheduler load balancing for
compute CS
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Start to use the scheduler load balancing for userspace compute
command submissions.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index 3ff8042b8f89..a078e68e0319 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -49,7 +49,8 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
struct amdgpu_ctx *ctx)
{
struct drm_sched_rq *sdma_rqs[AMDGPU_MAX_RINGS];
- unsigned i, j, num_sdma_rqs;
+ struct drm_sched_rq *comp_rqs[AMDGPU_MAX_RINGS];
+ unsigned i, j, num_sdma_rqs, num_comp_rqs;
int r;
if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX)
@@ -82,6 +83,7 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;
num_sdma_rqs = 0;
+ num_comp_rqs = 0;
for (i = 0; i < adev->num_rings; i++) {
struct amdgpu_ring *ring = adev->rings[i];
struct drm_sched_rq *rq;
@@ -89,6 +91,8 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
rq = &ring->sched.sched_rq[priority];
if (ring->funcs->type == AMDGPU_RING_TYPE_SDMA)
sdma_rqs[num_sdma_rqs++] = rq;
+ else if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
+ comp_rqs[num_comp_rqs++] = rq;
}
/* create context entity for each ring */
@@ -102,6 +106,10 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev,
r = drm_sched_entity_init(&ctx->rings[i].entity,
sdma_rqs, num_sdma_rqs,
&ctx->guilty);
+ } else if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
+ r = drm_sched_entity_init(&ctx->rings[i].entity,
+ comp_rqs, num_comp_rqs,
+ &ctx->guilty);
} else {
struct drm_sched_rq *rq;
--
2.17.1
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