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From 80af675df21a4ea19fa7d81f929af7685501fc8f Mon Sep 17 00:00:00 2001
From: Hawking Zhang <Hawking.Zhang@amd.com>
Date: Mon, 12 Mar 2018 18:25:15 +0800
Subject: [PATCH 3887/4131] drm/amdgpu/soc15: initialize reg base for vega12
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index e308c3c..51cf8a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -508,6 +508,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
/* Set IP register base before any HW register access */
switch (adev->asic_type) {
case CHIP_VEGA10:
+ case CHIP_VEGA12:
case CHIP_RAVEN:
vega10_reg_base_init(adev);
break;
--
2.7.4
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