1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
|
From 199fad30a618dd6c94bb1e188beab0dd1a81ea16 Mon Sep 17 00:00:00 2001
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Date: Tue, 9 Jan 2018 16:37:03 -0500
Subject: [PATCH 3260/4131] drm/amd/display: revert to hacking bounding box for
pipe split
Directly editing pipe config outside of formula is error prone
and results in higher clocks being used when splitting.
For this reason we reverted to using bounding box hacking
to split. Since sometimes this erroneusly results in higher dpm
being required we unhack the bounding box and recalculate to allow
dpm0 is possible.
Side effect is we will lose some stutter efficiency
in non dpm0 cases. This is not a big concern since increased stutter
efficiency saves an order of magnitude less power than lower dpm.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 43 ++++++++++--------------
1 file changed, 18 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index c6a7507..c9aa686 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -626,7 +626,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
return updated;
}
-void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
+static void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
{
/*
* disable optional pipe split by lower dispclk bounding box
@@ -635,7 +635,7 @@ void hack_disable_optional_pipe_split(struct dcn_bw_internal_vars *v)
v->max_dispclk[0] = v->max_dppclk_vmin0p65;
}
-void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
+static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
unsigned int pixel_rate_khz)
{
float pixel_rate_mhz = pixel_rate_khz / 1000;
@@ -648,25 +648,20 @@ void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
v->max_dppclk[0] = pixel_rate_mhz;
}
-void hack_bounding_box(struct dcn_bw_internal_vars *v,
+static void hack_bounding_box(struct dcn_bw_internal_vars *v,
struct dc_debug *dbg,
struct dc_state *context)
{
- if (dbg->pipe_split_policy == MPC_SPLIT_AVOID) {
+ if (dbg->pipe_split_policy == MPC_SPLIT_AVOID)
hack_disable_optional_pipe_split(v);
- }
if (dbg->pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP &&
- context->stream_count >= 2) {
+ context->stream_count >= 2)
hack_disable_optional_pipe_split(v);
- }
if (context->stream_count == 1 &&
- dbg->force_single_disp_pipe_split) {
- struct dc_stream_state *stream0 = context->streams[0];
-
- hack_force_pipe_split(v, stream0->timing.pix_clk_khz);
- }
+ dbg->force_single_disp_pipe_split)
+ hack_force_pipe_split(v, context->streams[0]->timing.pix_clk_khz);
}
bool dcn_validate_bandwidth(
@@ -800,23 +795,10 @@ bool dcn_validate_bandwidth(
v->phyclk_per_state[2] = v->phyclkv_nom0p8;
v->phyclk_per_state[1] = v->phyclkv_mid0p72;
v->phyclk_per_state[0] = v->phyclkv_min0p65;
-
- hack_bounding_box(v, &dc->debug, context);
-
- if (v->voltage_override == dcn_bw_v_max0p9) {
- v->voltage_override_level = number_of_states - 1;
- } else if (v->voltage_override == dcn_bw_v_nom0p8) {
- v->voltage_override_level = number_of_states - 2;
- } else if (v->voltage_override == dcn_bw_v_mid0p72) {
- v->voltage_override_level = number_of_states - 3;
- } else {
- v->voltage_override_level = 0;
- }
v->synchronized_vblank = dcn_bw_no;
v->ta_pscalculation = dcn_bw_override;
v->allow_different_hratio_vratio = dcn_bw_yes;
-
for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
@@ -949,8 +931,19 @@ bool dcn_validate_bandwidth(
v->number_of_active_planes = input_idx;
scaler_settings_calculation(v);
+
+ hack_bounding_box(v, &dc->debug, context);
+
mode_support_and_system_configuration(v);
+ /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */
+ if (v->voltage_level != 0
+ && context->stream_count == 1
+ && dc->debug.force_single_disp_pipe_split) {
+ v->max_dppclk[0] = v->max_dppclk_vmin0p65;
+ mode_support_and_system_configuration(v);
+ }
+
if (v->voltage_level == 0 &&
(dc->debug.sr_exit_time_dpm0_ns
|| dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {
--
2.7.4
|
