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From 014acf7d1b5b1edcabce9e99ebadc168571197fa Mon Sep 17 00:00:00 2001
From: Yue Hin Lau <Yuehin.Lau@amd.com>
Date: Thu, 23 Nov 2017 11:32:18 -0500
Subject: [PATCH 2920/4131] drm/amd/display: dpp clean up
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 4 +++-
drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 7 +------
2 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index 4c90043..4f51253 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -49,6 +49,8 @@
#define FN(reg_name, field_name) \
dpp->tf_shift->field_name, dpp->tf_mask->field_name
+#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
+
struct dcn10_input_csc_matrix {
enum dc_color_space color_space;
uint16_t regval[12];
@@ -270,7 +272,7 @@ void dpp1_cm_set_output_csc_default(
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
struct out_csc_color_matrix tbl_entry;
int i, j;
- int arr_size = sizeof(output_csc_matrix) / sizeof(struct output_csc_matrix);
+ int arr_size = NUM_ELEMENTS(output_csc_matrix);
uint32_t ocsc_mode = 4;
tbl_entry.color_space = colorspace;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index d7d027c..0f70f36 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -131,12 +131,7 @@ struct out_csc_color_matrix {
uint16_t regval[12];
};
-struct output_csc_matrix {
- enum dc_color_space color_space;
- uint16_t regval[12];
-};
-
-static const struct output_csc_matrix output_csc_matrix[] = {
+static const struct out_csc_color_matrix output_csc_matrix[] = {
{ COLOR_SPACE_SRGB,
{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
{ COLOR_SPACE_SRGB_LIMITED,
--
2.7.4
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