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From 80207cba6a513edfede5fb4d97dc03019900a5b3 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Tue, 23 Aug 2016 17:37:36 -0400
Subject: [PATCH 1361/4131] drm/amdgpu/gfx8: disable EDC
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index c8330d9..93d750f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1689,7 +1689,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
goto fail;
}
-
+#if 0
tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2);
tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1);
WREG32(mmGB_EDC_MODE, tmp);
@@ -1697,7 +1697,7 @@ static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev)
tmp = RREG32(mmCC_GC_EDC_CONFIG);
tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0) | 1;
WREG32(mmCC_GC_EDC_CONFIG, tmp);
-
+#endif
/* read back registers to clear the counters */
for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers); i++)
--
2.7.4
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