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From f381c919380156eb6094faa33733a0ba3c71d290 Mon Sep 17 00:00:00 2001
From: Corbin McElhanney <corbin.mcelhanney@amd.com>
Date: Fri, 4 Aug 2017 15:30:45 -0400
Subject: [PATCH 0745/4131] drm/amd/display: Fix hw state logging regression
Signed-off-by: Corbin McElhanney <corbin.mcelhanney@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 292dfef..2fd9c33 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -134,6 +134,7 @@ static void verify_allow_pstate_change_high(
static unsigned int pstate_wait_timeout_us = 40;
static unsigned int max_sampled_pstate_wait_us; /* data collection */
static bool forced_pstate_allow; /* help with revert wa */
+ static bool should_log_hw_state; /* prevent hw state log by default */
unsigned int debug_index = 0x7;
unsigned int debug_data;
@@ -191,7 +192,9 @@ static void verify_allow_pstate_change_high(
REG_WRITE(DCHUBBUB_ARB_DRAM_STATE_CNTL, force_allow_pstate);
forced_pstate_allow = true;
- dcn10_log_hw_state(DC_TO_CORE(hws->ctx->dc));
+ if (should_log_hw_state) {
+ dcn10_log_hw_state(DC_TO_CORE(hws->ctx->dc));
+ }
BREAK_TO_DEBUGGER();
}
--
2.7.4
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