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From b97f2ae47a348d5dbe0baa3d32a8014f16178dae Mon Sep 17 00:00:00 2001
From: Charlene Liu <charlene.liu@amd.com>
Date: Tue, 11 Jul 2017 13:40:52 -0400
Subject: [PATCH 0604/4131] drm/amd/display: change non_dpm0 state's default SR
latency
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index a1eabc4..0ea0dab 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -37,8 +37,8 @@
/* Defaults from spreadsheet rev#247 */
const struct dcn_soc_bounding_box dcn10_soc_defaults = {
/* latencies */
- .sr_exit_time = 17, /*us*/
- .sr_enter_plus_exit_time = 19, /*us*/
+ .sr_exit_time = 13, /*us*/
+ .sr_enter_plus_exit_time = 15, /*us*/
.urgent_latency = 4, /*us*/
.dram_clock_change_latency = 17, /*us*/
.write_back_latency = 12, /*us*/
--
2.7.4
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