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From 269c5b3f9b7339ea5c4e1fc4eb699d1b3662dd4c Mon Sep 17 00:00:00 2001
From: Charlene Liu <charlene.liu@amd.com>
Date: Tue, 30 Apr 2019 13:01:12 -0400
Subject: [PATCH 2527/2940] drm/amd/display: Create DWB resource for DCN2
[Description]
dcn20 has num_dwb =1 in the res cap, but not created.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Duke Du <Duke.Du@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn20/Makefile | 1 -
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 111 ++++++++++++++++++
.../drm/amd/display/include/logger_types.h | 3 +
.../include/asic_reg/dcn/dcn_2_0_0_offset.h | 4 +
.../include/asic_reg/dcn/dcn_2_0_0_sh_mask.h | 16 +++
5 files changed, 134 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
index a6299f0d6b22..1b68de27ba74 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/Makefile
@@ -10,7 +10,6 @@ ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
DCN20 += dcn20_dsc.o
endif
-
CFLAGS_dcn20_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
AMD_DAL_DCN20 = $(addprefix $(AMDDALPATH)/dc/dcn20/,$(DCN20))
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index ceee0d6b3c26..46e7f76a6553 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -64,6 +64,9 @@
#include "nbio/nbio_2_3_offset.h"
+#include "dcn20/dcn20_dwb.h"
+#include "dcn20/dcn20_mmhubbub.h"
+
#include "mmhub/mmhub_2_0_0_offset.h"
#include "mmhub/mmhub_2_0_0_sh_mask.h"
@@ -470,6 +473,40 @@ static const struct dcn2_dpp_mask tf_mask = {
TF_REG_LIST_SH_MASK_DCN20(_MASK)
};
+#define dwbc_regs_dcn2(id)\
+[id] = {\
+ DWBC_COMMON_REG_LIST_DCN2_0(id),\
+ }
+
+static const struct dcn20_dwbc_registers dwbc20_regs[] = {
+ dwbc_regs_dcn2(0),
+};
+
+static const struct dcn20_dwbc_shift dwbc20_shift = {
+ DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
+};
+
+static const struct dcn20_dwbc_mask dwbc20_mask = {
+ DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
+};
+
+#define mcif_wb_regs_dcn2(id)\
+[id] = {\
+ MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
+ }
+
+static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
+ mcif_wb_regs_dcn2(0),
+};
+
+static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
+ MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
+};
+
+static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
+ MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
+};
+
static const struct dcn20_mpc_registers mpc_regs = {
MPC_REG_LIST_DCN2_0(0),
MPC_REG_LIST_DCN2_0(1),
@@ -1088,6 +1125,17 @@ static void destruct(struct dcn20_resource_pool *pool)
}
}
+ for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
+ if (pool->base.dwbc[i] != NULL) {
+ kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
+ pool->base.dwbc[i] = NULL;
+ }
+ if (pool->base.mcif_wb[i] != NULL) {
+ kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
+ pool->base.mcif_wb[i] = NULL;
+ }
+ }
+
for (i = 0; i < pool->base.audio_count; i++) {
if (pool->base.audios[i])
dce_aud_destroy(&pool->base.audios[i]);
@@ -2384,6 +2432,58 @@ static struct resource_funcs dcn20_res_pool_funcs = {
#endif
};
+bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+ int i;
+ uint32_t pipe_count = pool->res_cap->num_dwb;
+
+ ASSERT(pipe_count > 0);
+
+ for (i = 0; i < pipe_count; i++) {
+ struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
+ GFP_KERNEL);
+
+ if (!dwbc20) {
+ dm_error("DC: failed to create dwbc20!\n");
+ return false;
+ }
+ dcn20_dwbc_construct(dwbc20, ctx,
+ &dwbc20_regs[i],
+ &dwbc20_shift,
+ &dwbc20_mask,
+ i);
+ pool->dwbc[i] = &dwbc20->base;
+ }
+ return true;
+}
+
+bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
+{
+ int i;
+ uint32_t pipe_count = pool->res_cap->num_dwb;
+
+ ASSERT(pipe_count > 0);
+
+ for (i = 0; i < pipe_count; i++) {
+ struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
+ GFP_KERNEL);
+
+ if (!mcif_wb20) {
+ dm_error("DC: failed to create mcif_wb20!\n");
+ return false;
+ }
+
+ dcn20_mmhubbub_construct(mcif_wb20, ctx,
+ &mcif_wb20_regs[i],
+ &mcif_wb20_shift,
+ &mcif_wb20_mask,
+ i);
+
+ pool->mcif_wb[i] = &mcif_wb20->base;
+ }
+ return true;
+}
+
struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
{
struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
@@ -2972,6 +3072,17 @@ static bool construct(
}
#endif
+ if (!dcn20_dwbc_create(ctx, &pool->base)) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create dwbc!\n");
+ goto create_fail;
+ }
+ if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
+ BREAK_TO_DEBUGGER();
+ dm_error("DC: failed to create mcif_wb!\n");
+ goto create_fail;
+ }
+
if (!resource_construct(num_virtual_links, dc, &pool->base,
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
&res_create_funcs : &res_create_maximus_funcs)))
diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h
index 22ba83f228cf..78252240ab83 100644
--- a/drivers/gpu/drm/amd/display/include/logger_types.h
+++ b/drivers/gpu/drm/amd/display/include/logger_types.h
@@ -66,6 +66,9 @@
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
#define DC_LOG_DSC(...) DRM_DEBUG_KMS(__VA_ARGS__)
#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0) || defined(CONFIG_DRM_AMD_DC_DCN2_0)
+#define DC_LOG_DWB(...) DRM_DEBUG_KMS(__VA_ARGS__)
+#endif
struct dal_logger;
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h
index e3188516cfbf..cff8f91555d3 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_offset.h
@@ -889,6 +889,8 @@
#define mmCNV_TEST_CRC_BLUE_BASE_IDX 2
#define mmWB_DEBUG_CTRL 0x01f2
#define mmWB_DEBUG_CTRL_BASE_IDX 2
+#define mmWB_DBG_MODE 0x01f3
+#define mmWB_DBG_MODE_BASE_IDX 2
#define mmWB_HW_DEBUG 0x01f4
#define mmWB_HW_DEBUG_BASE_IDX 2
#define mmWB_SOFT_RESET 0x01f5
@@ -1065,6 +1067,8 @@
#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x02d9
#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
+#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL 0x02da
+#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x02db
#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x02dc
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h
index 5e78f741c053..10c83fecd147 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h
@@ -5999,6 +5999,19 @@
#define WB_DEBUG_CTRL__WB_DEBUG_SEL__SHIFT 0x6
#define WB_DEBUG_CTRL__WB_DEBUG_EN_MASK 0x00000001L
#define WB_DEBUG_CTRL__WB_DEBUG_SEL_MASK 0x000000C0L
+//WB_DBG_MODE
+#define WB_DBG_MODE__WB_DBG_MODE_EN__SHIFT 0x0
+#define WB_DBG_MODE__WB_DBG_DIN_FMT__SHIFT 0x1
+#define WB_DBG_MODE__WB_DBG_36MODE__SHIFT 0x2
+#define WB_DBG_MODE__WB_DBG_CMAP__SHIFT 0x3
+#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR__SHIFT 0x8
+#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH__SHIFT 0x10
+#define WB_DBG_MODE__WB_DBG_MODE_EN_MASK 0x00000001L
+#define WB_DBG_MODE__WB_DBG_DIN_FMT_MASK 0x00000002L
+#define WB_DBG_MODE__WB_DBG_36MODE_MASK 0x00000004L
+#define WB_DBG_MODE__WB_DBG_CMAP_MASK 0x00000008L
+#define WB_DBG_MODE__WB_DBG_PXLRATE_ERROR_MASK 0x00000100L
+#define WB_DBG_MODE__WB_DBG_SOURCE_WIDTH_MASK 0x7FFF0000L
//WB_HW_DEBUG
#define WB_HW_DEBUG__WB_HW_DEBUG__SHIFT 0x0
#define WB_HW_DEBUG__WB_HW_DEBUG_MASK 0xFFFFFFFFL
@@ -6646,6 +6659,9 @@
//MCIF_WB0_MULTI_LEVEL_QOS_CTRL
#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT__SHIFT 0x0
#define MCIF_WB0_MULTI_LEVEL_QOS_CTRL__MAX_SCALED_TIME_TO_URGENT_MASK 0x003FFFFFL
+//MCIF_WB0_MCIF_WB_SECURITY_LEVEL
+#define MCIF_WB0_MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL__SHIFT 0x0
+#define MCIF_WB0_MCIF_WB_SECURITY_LEVEL__MCIF_WB_SECURITY_LEVEL_MASK 0x00000007L
//MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE
#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE__SHIFT 0x0
#define MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE__MCIF_WB_BUF_LUMA_SIZE_MASK 0x000FFFFFL
--
2.17.1
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