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From 90e0e6a8387acd3d4b92ac00fcc523010e3292e4 Mon Sep 17 00:00:00 2001
From: Kevin Wang <kevin1.wang@amd.com>
Date: Thu, 30 May 2019 00:14:14 -0500
Subject: [PATCH 2361/2940] drm/amd/powerplay: add function
get_workload_type_map for swsmu
1.add new callback function get_workload_byte for smu
2.remove old workload map function
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 6 +-
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 3 +
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 23 ++++++++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 58 ++++++++-----------
4 files changed, 53 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 0275c4b96c9a..b62d272380d5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -532,6 +532,7 @@ struct pptable_funcs {
int (*get_smu_feature_index)(struct smu_context *smu, uint32_t index);
int (*get_smu_table_index)(struct smu_context *smu, uint32_t index);
int (*get_smu_power_index)(struct smu_context *smu, uint32_t index);
+ int (*get_workload_type)(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile);
int (*run_afll_btc)(struct smu_context *smu);
int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num);
enum amd_pm_state_type (*get_current_power_state)(struct smu_context *smu);
@@ -563,7 +564,6 @@ struct pptable_funcs {
*clocks);
int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
- int (*conv_profile_to_workload )(struct smu_context *smu, int power_profile);
enum amd_dpm_forced_level (*get_performance_level)(struct smu_context *smu);
int (*force_performance_level)(struct smu_context *smu, enum amd_dpm_forced_level level);
int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
@@ -839,6 +839,8 @@ struct smu_funcs
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_table_index? (smu)->ppt_funcs->get_smu_table_index((smu), (tab)) : -EINVAL) : -EINVAL)
#define smu_power_get_index(smu, src) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_power_index? (smu)->ppt_funcs->get_smu_power_index((smu), (src)) : -EINVAL) : -EINVAL)
+#define smu_workload_get_type(smu, profile) \
+ ((smu)->ppt_funcs? ((smu)->ppt_funcs->get_workload_type? (smu)->ppt_funcs->get_workload_type((smu), (profile)) : -EINVAL) : -EINVAL)
#define smu_run_afll_btc(smu) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->run_afll_btc? (smu)->ppt_funcs->run_afll_btc((smu)) : 0) : 0)
#define smu_get_allowed_feature_mask(smu, feature_mask, num) \
@@ -869,8 +871,6 @@ struct smu_funcs
((smu)->funcs->notify_smu_enable_pwe ? (smu)->funcs->notify_smu_enable_pwe((smu)) : 0)
#define smu_set_watermarks_for_clock_ranges(smu, clock_ranges) \
((smu)->funcs->set_watermarks_for_clock_ranges ? (smu)->funcs->set_watermarks_for_clock_ranges((smu), (clock_ranges)) : 0)
-#define smu_conv_profile_to_workload(smu, type) \
- ((smu)->ppt_funcs->conv_profile_to_workload ? (smu)->ppt_funcs->conv_profile_to_workload((smu), (type)) : 0)
#define smu_dpm_set_uvd_enable(smu, enable) \
((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
#define smu_dpm_set_vce_enable(smu, enable) \
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 3a1f6f790795..d93cd76269b4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -54,6 +54,9 @@
#define PWR_MAP(tab) \
[SMU_POWER_SOURCE_##tab] = POWER_SOURCE_##tab
+#define WORKLOAD_MAP(profile, workload) \
+ [profile] = workload
+
struct smu_11_0_max_sustainable_clocks {
uint32_t display_clock;
uint32_t phy_clock;
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 1219a68e56f2..979ed6b1c8df 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -194,6 +194,16 @@ static int navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
PWR_MAP(DC),
};
+static int navi10_workload_map[] = {
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
+};
+
static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index)
{
int val;
@@ -259,6 +269,18 @@ static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index)
return val;
}
+
+static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
+{
+ int val;
+ if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
+ return -EINVAL;
+
+ val = navi10_workload_map[profile];
+
+ return val;
+}
+
static int
navi10_get_allowed_feature_mask(struct smu_context *smu,
uint32_t *feature_mask, uint32_t num)
@@ -848,6 +870,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.get_smu_feature_index = navi10_get_smu_feature_index,
.get_smu_table_index = navi10_get_smu_table_index,
.get_smu_power_index= navi10_get_pwr_src_index,
+ .get_workload_type = navi10_get_workload_type,
.get_allowed_feature_mask = navi10_get_allowed_feature_mask,
.set_default_dpm_table = navi10_set_default_dpm_table,
.dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 2f33fec4da98..7fed65a9c00c 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -207,6 +207,16 @@ static int vega20_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
PWR_MAP(DC),
};
+static int vega20_workload_map[] = {
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_DEFAULT_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT),
+ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
+};
+
static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index)
{
int val;
@@ -273,6 +283,17 @@ static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index)
return val;
}
+static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_PROFILE profile)
+{
+ int val;
+ if (profile > PP_SMC_POWER_PROFILE_CUSTOM)
+ return -EINVAL;
+
+ val = vega20_workload_map[profile];
+
+ return val;
+}
+
static void vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
{
SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
@@ -1669,37 +1690,6 @@ static int vega20_get_od_percentage(struct smu_context *smu,
return value;
}
-static int vega20_conv_profile_to_workload(struct smu_context *smu, int power_profile)
-{
- int pplib_workload = 0;
-
- switch (power_profile) {
- case PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT:
- pplib_workload = WORKLOAD_DEFAULT_BIT;
- break;
- case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
- pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
- break;
- case PP_SMC_POWER_PROFILE_POWERSAVING:
- pplib_workload = WORKLOAD_PPLIB_POWER_SAVING_BIT;
- break;
- case PP_SMC_POWER_PROFILE_VIDEO:
- pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
- break;
- case PP_SMC_POWER_PROFILE_VR:
- pplib_workload = WORKLOAD_PPLIB_VR_BIT;
- break;
- case PP_SMC_POWER_PROFILE_COMPUTE:
- pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
- break;
- case PP_SMC_POWER_PROFILE_CUSTOM:
- pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
- break;
- }
-
- return pplib_workload;
-}
-
static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
{
DpmActivityMonitorCoeffInt_t activity_monitor;
@@ -1736,7 +1726,7 @@ static int vega20_get_power_profile_mode(struct smu_context *smu, char *buf)
for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
- workload_type = smu_conv_profile_to_workload(smu, i);
+ workload_type = smu_workload_get_type(smu, i);
result = smu_update_table(smu,
TABLE_ACTIVITY_MONITOR_COEFF | workload_type << 16,
(void *)(&activity_monitor), false);
@@ -1888,7 +1878,7 @@ static int vega20_set_power_profile_mode(struct smu_context *smu, long *input, u
}
/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
- workload_type = smu_conv_profile_to_workload(smu, smu->power_profile_mode);
+ workload_type = smu_workload_get_type(smu, smu->power_profile_mode);
smu_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1 << workload_type);
@@ -3114,6 +3104,7 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.get_smu_feature_index = vega20_get_smu_feature_index,
.get_smu_table_index = vega20_get_smu_table_index,
.get_smu_power_index = vega20_get_pwr_src_index,
+ .get_workload_type = vega20_get_workload_type,
.run_afll_btc = vega20_run_btc_afll,
.get_allowed_feature_mask = vega20_get_allowed_feature_mask,
.get_current_power_state = vega20_get_current_power_state,
@@ -3125,7 +3116,6 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.get_clock_by_type_with_latency = vega20_get_clock_by_type_with_latency,
.set_default_od8_settings = vega20_set_default_od8_setttings,
.get_od_percentage = vega20_get_od_percentage,
- .conv_profile_to_workload = vega20_conv_profile_to_workload,
.get_power_profile_mode = vega20_get_power_profile_mode,
.set_power_profile_mode = vega20_set_power_profile_mode,
.get_performance_level = vega20_get_performance_level,
--
2.17.1
|
