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From c9d4a02bf4ba2bc98fc56f562be85dac683f9a41 Mon Sep 17 00:00:00 2001
From: Hawking Zhang <Hawking.Zhang@amd.com>
Date: Sun, 3 Mar 2019 11:02:58 +0800
Subject: [PATCH 2129/2940] drm/amdgpu: add CLK 11.0 register headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../include/asic_reg/clk/clk_11_0_0_offset.h | 33 ++++++++++++++++
.../include/asic_reg/clk/clk_11_0_0_sh_mask.h | 38 +++++++++++++++++++
2 files changed, 71 insertions(+)
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h
diff --git a/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_offset.h
new file mode 100644
index 000000000000..63759f8c0fa2
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_offset.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _clk_11_0_0_OFFSET_HEADER
+#define _clk_11_0_0_OFFSET_HEADER
+
+
+// addressBlock: clk_clk3_0_SmuClkDec
+// base address: 0x5c800
+#define mmCLK3_0_CLK3_CLK_PLL_REQ 0x000e
+#define mmCLK3_0_CLK3_CLK_PLL_REQ_BASE_IDX 3
+#define mmCLK3_0_CLK3_CLK2_DFS_CNTL 0x0054
+#define mmCLK3_0_CLK3_CLK2_DFS_CNTL_BASE_IDX 3
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h
new file mode 100644
index 000000000000..e3d954434fcc
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_0_sh_mask.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef _clk_11_0_0_SH_MASK_HEADER
+#define _clk_11_0_0_SH_MASK_HEADER
+
+
+// addressBlock: clk_clk3_0_SmuClkDec
+//CLK3_0_CLK3_CLK_PLL_REQ
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
+#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
+#define CLK3_0_CLK3_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
+#define CLK3_0_CLK3_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
+//CLK3_0_CLK3_CLK2_DFS_CNTL
+#define CLK3_0_CLK3_CLK2_DFS_CNTL__CLK2_DIVIDER__SHIFT 0x0
+#define CLK3_0_CLK3_CLK2_DFS_CNTL__CLK2_DIVIDER_MASK 0x0000007FL
+
+
+#endif
--
2.17.1
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