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From 9db46a77e3de5b313ac36ab59ae6d0a176dc79ec Mon Sep 17 00:00:00 2001
From: Trigger Huang <Trigger.Huang@amd.com>
Date: Mon, 3 Jun 2019 16:48:17 +0800
Subject: [PATCH 2052/2940] drm/amdgpu: Hardcode reg access using L1 security
Under Vega10 SR-IOV VF, L1 register access mode should be enabled by
default as the non-security VF will no longer be supported.
Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
index 31030f86be86..235548c0b41f 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
@@ -451,19 +451,16 @@ void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev)
static void xgpu_ai_init_reg_access_mode(struct amdgpu_device *adev)
{
- uint32_t rlc_fw_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
- uint32_t sos_fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);
-
adev->virt.reg_access_mode = AMDGPU_VIRT_REG_ACCESS_LEGACY;
- if (rlc_fw_ver >= 0x5d)
- adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_RLC;
+ /* Enable L1 security reg access mode by defaul, as non-security VF
+ * will no longer be supported.
+ */
+ adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_RLC;
- if (sos_fw_ver >= 0x80455)
- adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH;
+ adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH;
- if (sos_fw_ver >= 0x8045b)
- adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_SKIP_SEETING;
+ adev->virt.reg_access_mode |= AMDGPU_VIRT_REG_SKIP_SEETING;
}
const struct amdgpu_virt_ops xgpu_ai_virt_ops = {
--
2.17.1
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