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From 5bf091c5028d5b254ef1d80b8252b02e3f8dc49f Mon Sep 17 00:00:00 2001
From: Likun Gao <Likun.Gao@amd.com>
Date: Tue, 25 Dec 2018 14:44:25 +0800
Subject: [PATCH 1397/2940] drm/amd/powerplay: add function to get power limit
for smu11 (v2)
Add smu_v11_0_get_power_limit function to get power limit vaule.
v2: update "set" to "get", it only implements "get" behavior. (Alex)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 ++++
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 7 ++++++-
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 20 +++++++++++++++++++
3 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index f5ffc9bd31a6..b225cf876a91 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -397,6 +397,10 @@ static int smu_smc_table_hw_init(struct smu_context *smu)
if (ret)
return ret;
+ ret = smu_get_power_limit(smu);
+ if (ret)
+ return ret;
+
/*
* Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
*/
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 94013c5ca2e3..db3d0f57c5ca 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -201,6 +201,9 @@ struct smu_context
uint32_t pstate_sclk;
uint32_t pstate_mclk;
+
+ uint32_t power_limit;
+ uint32_t default_power_limit;
};
struct pptable_funcs {
@@ -247,7 +250,7 @@ struct smu_funcs
int (*enable_all_mask)(struct smu_context *smu);
int (*disable_all_mask)(struct smu_context *smu);
int (*notify_display_change)(struct smu_context *smu);
-
+ int (*get_power_limit)(struct smu_context *smu);
};
#define smu_init_microcode(smu) \
@@ -322,6 +325,8 @@ struct smu_funcs
((smu)->ppt_funcs->set_default_dpm_table ? (smu)->ppt_funcs->set_default_dpm_table((smu)) : 0)
#define smu_populate_umd_state_clk(smu) \
((smu)->ppt_funcs->populate_umd_state_clk ? (smu)->ppt_funcs->populate_umd_state_clk((smu)) : 0)
+#define smu_get_power_limit(smu) \
+ ((smu)->funcs->get_power_limit? (smu)->funcs->get_power_limit((smu)) : 0)
#define smu_msg_get_index(smu, msg) \
((smu)->ppt_funcs? ((smu)->ppt_funcs->get_smu_msg_index? (smu)->ppt_funcs->get_smu_msg_index((smu), (msg)) : -EINVAL) : -EINVAL)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 66af3e61d33a..491986713774 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -738,6 +738,25 @@ static int smu_v11_0_notify_display_change(struct smu_context *smu)
return ret;
}
+static int smu_v11_0_get_power_limit(struct smu_context *smu)
+{
+ int ret;
+ uint32_t power_limit_value;
+
+ ret = smu_send_smc_msg_with_param(smu,
+ SMU_MSG_GetPptLimit,
+ POWER_SOURCE_AC << 16);
+ if (ret) {
+ pr_err("[GetPptLimit] get default PPT limit failed!");
+ return ret;
+ }
+
+ smu_read_smc_arg(smu, &power_limit_value);
+ smu->power_limit = smu->default_power_limit = power_limit_value;
+
+ return 0;
+}
+
static const struct smu_funcs smu_v11_0_funcs = {
.init_microcode = smu_v11_0_init_microcode,
.load_microcode = smu_v11_0_load_microcode,
@@ -766,6 +785,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.enable_all_mask = smu_v11_0_enable_all_mask,
.disable_all_mask = smu_v11_0_disable_all_mask,
.notify_display_change = smu_v11_0_notify_display_change,
+ .get_power_limit = smu_v11_0_get_power_limit,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.17.1
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