1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
|
From f3481b567f1812f41d0c8fd15b01f76114d88b57 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
Date: Fri, 1 Feb 2019 15:32:55 -0500
Subject: [PATCH 1183/2940] Revert "drm/amd/powerplay: support Vega10 SOCclk
and DCEFclk dpm level settings"
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This reverts commit 42a2d4839bc4f095621d259a3ff5401063b914cc.
https://bugs.freedesktop.org/show_bug.cgi?id=109462
Acked by Alex Deucher.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
---
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 83 -------------------
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 1 -
2 files changed, 84 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 0a5f7df3acc2..19bb43b1fdb1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -72,21 +72,6 @@ static const uint32_t channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
#define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L
#define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
-typedef enum {
- CLK_SMNCLK = 0,
- CLK_SOCCLK,
- CLK_MP0CLK,
- CLK_MP1CLK,
- CLK_LCLK,
- CLK_DCEFCLK,
- CLK_VCLK,
- CLK_DCLK,
- CLK_ECLK,
- CLK_UCLK,
- CLK_GFXCLK,
- CLK_COUNT,
-} CLOCK_ID_e;
-
static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
struct vega10_power_state *cast_phw_vega10_power_state(
@@ -3501,17 +3486,6 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
}
}
- if (!data->registry_data.socclk_dpm_key_disabled) {
- if (data->smc_state_table.soc_boot_level !=
- data->dpm_table.soc_table.dpm_state.soft_min_level) {
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_SetSoftMinSocclkByIndex,
- data->smc_state_table.soc_boot_level);
- data->dpm_table.soc_table.dpm_state.soft_min_level =
- data->smc_state_table.soc_boot_level;
- }
- }
-
return 0;
}
@@ -3543,17 +3517,6 @@ static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
}
}
- if (!data->registry_data.socclk_dpm_key_disabled) {
- if (data->smc_state_table.soc_max_level !=
- data->dpm_table.soc_table.dpm_state.soft_max_level) {
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_SetSoftMaxSocclkByIndex,
- data->smc_state_table.soc_max_level);
- data->dpm_table.soc_table.dpm_state.soft_max_level =
- data->smc_state_table.soc_max_level;
- }
- }
-
return 0;
}
@@ -4066,24 +4029,6 @@ static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
break;
- case PP_SOCCLK:
- data->smc_state_table.soc_boot_level = mask ? (ffs(mask) - 1) : 0;
- data->smc_state_table.soc_max_level = mask ? (fls(mask) - 1) : 0;
-
- PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
- "Failed to upload boot level to lowest!",
- return -EINVAL);
-
- PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
- "Failed to upload dpm max level to highest!",
- return -EINVAL);
-
- break;
-
- case PP_DCEFCLK:
- pr_info("Setting DCEFCLK min/max dpm level is not supported!\n");
- break;
-
case PP_PCIE:
default:
break;
@@ -4428,8 +4373,6 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
struct vega10_hwmgr *data = hwmgr->backend;
struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
- struct vega10_single_dpm_table *soc_table = &(data->dpm_table.soc_table);
- struct vega10_single_dpm_table *dcef_table = &(data->dpm_table.dcef_table);
struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table);
struct vega10_odn_clock_voltage_dependency_table *podn_vdd_dep = NULL;
@@ -4460,32 +4403,6 @@ static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
i, mclk_table->dpm_levels[i].value / 100,
(i == now) ? "*" : "");
break;
- case PP_SOCCLK:
- if (data->registry_data.socclk_dpm_key_disabled)
- break;
-
- smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex);
- now = smum_get_argument(hwmgr);
-
- for (i = 0; i < soc_table->count; i++)
- size += sprintf(buf + size, "%d: %uMhz %s\n",
- i, soc_table->dpm_levels[i].value / 100,
- (i == now) ? "*" : "");
- break;
- case PP_DCEFCLK:
- if (data->registry_data.dcefclk_dpm_key_disabled)
- break;
-
- smum_send_msg_to_smc_with_parameter(hwmgr,
- PPSMC_MSG_GetClockFreqMHz, CLK_DCEFCLK);
- now = smum_get_argument(hwmgr);
-
- for (i = 0; i < dcef_table->count; i++)
- size += sprintf(buf + size, "%d: %uMhz %s\n",
- i, dcef_table->dpm_levels[i].value / 100,
- (dcef_table->dpm_levels[i].value / 100 == now) ?
- "*" : "");
- break;
case PP_PCIE:
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex);
now = smum_get_argument(hwmgr);
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
index f752b4ad0c8a..89870556de1b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
@@ -199,7 +199,6 @@ struct vega10_smc_state_table {
uint32_t vce_boot_level;
uint32_t gfx_max_level;
uint32_t mem_max_level;
- uint32_t soc_max_level;
uint8_t vr_hot_gpio;
uint8_t ac_dc_gpio;
uint8_t therm_out_gpio;
--
2.17.1
|
