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From 1bbbc73cd48090c0a48d4c26bfd262f9dd00eee3 Mon Sep 17 00:00:00 2001
From: Kent Russell <kent.russell@amd.com>
Date: Mon, 7 Jan 2019 06:02:06 -0500
Subject: [PATCH 1051/2940] drm/amdgpu: Add NBIO SMN headers v2
We need these offsets for PCIE perf counters, so include them as well as
the the previously-used defines from the nbio_*.c files
v2: Return NBIF definitions back to previous files
Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 6 +-
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 3 -
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 5 +-
.../amd/include/asic_reg/nbio/nbio_6_1_smn.h | 58 +++++++++++++++++++
.../amd/include/asic_reg/nbio/nbio_7_0_smn.h | 54 +++++++++++++++++
.../include/asic_reg/nbio/nbio_7_4_0_smn.h | 53 +++++++++++++++++
6 files changed, 167 insertions(+), 12 deletions(-)
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index accdedd63c98..1965756348bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -27,13 +27,9 @@
#include "nbio/nbio_6_1_default.h"
#include "nbio/nbio_6_1_offset.h"
#include "nbio/nbio_6_1_sh_mask.h"
+#include "nbio/nbio_6_1_smn.h"
#include "vega10_enum.h"
-#define smnCPM_CONTROL 0x11180460
-#define smnPCIE_CNTL2 0x11180070
-#define smnPCIE_CONFIG_CNTL 0x11180044
-#define smnPCIE_CI_CNTL 0x11180080
-
static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
{
u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
index 365517c0121e..c6b1c500368c 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
@@ -31,9 +31,6 @@
#define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c
-#define smnCPM_CONTROL 0x11180460
-#define smnPCIE_CNTL2 0x11180070
-
/* vega20 */
#define mmRCC_DEV0_EPF0_STRAP0_VG20 0x0011
#define mmRCC_DEV0_EPF0_STRAP0_VG20_BASE_IDX 2
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 4cd31a276dcd..0a613098337a 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -26,13 +26,10 @@
#include "nbio/nbio_7_4_offset.h"
#include "nbio/nbio_7_4_sh_mask.h"
+#include "nbio/nbio_7_4_0_smn.h"
#define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
-#define smnCPM_CONTROL 0x11180460
-#define smnPCIE_CNTL2 0x11180070
-#define smnPCIE_CI_CNTL 0x11180080
-
static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
{
u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
new file mode 100644
index 000000000000..8c75669eb500
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _nbio_6_1_SMN_HEADER
+#define _nbio_6_1_SMN_HEADER
+
+
+#define smnCPM_CONTROL 0x11180460
+#define smnPCIE_CNTL2 0x11180070
+#define smnPCIE_CONFIG_CNTL 0x11180044
+#define smnPCIE_CI_CNTL 0x11180080
+
+
+#define smnPCIE_PERF_COUNT_CNTL 0x11180200
+#define smnPCIE_PERF_CNTL_TXCLK 0x11180204
+#define smnPCIE_PERF_COUNT0_TXCLK 0x11180208
+#define smnPCIE_PERF_COUNT1_TXCLK 0x1118020c
+#define smnPCIE_PERF_CNTL_MST_R_CLK 0x11180210
+#define smnPCIE_PERF_COUNT0_MST_R_CLK 0x11180214
+#define smnPCIE_PERF_COUNT1_MST_R_CLK 0x11180218
+#define smnPCIE_PERF_CNTL_MST_C_CLK 0x1118021c
+#define smnPCIE_PERF_COUNT0_MST_C_CLK 0x11180220
+#define smnPCIE_PERF_COUNT1_MST_C_CLK 0x11180224
+#define smnPCIE_PERF_CNTL_SLV_R_CLK 0x11180228
+#define smnPCIE_PERF_COUNT0_SLV_R_CLK 0x1118022c
+#define smnPCIE_PERF_COUNT1_SLV_R_CLK 0x11180230
+#define smnPCIE_PERF_CNTL_SLV_S_C_CLK 0x11180234
+#define smnPCIE_PERF_COUNT0_SLV_S_C_CLK 0x11180238
+#define smnPCIE_PERF_COUNT1_SLV_S_C_CLK 0x1118023c
+#define smnPCIE_PERF_CNTL_SLV_NS_C_CLK 0x11180240
+#define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x11180244
+#define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x11180248
+#define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1118024c
+#define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x11180250
+#define smnPCIE_PERF_CNTL_TXCLK2 0x11180254
+#define smnPCIE_PERF_COUNT0_TXCLK2 0x11180258
+#define smnPCIE_PERF_COUNT1_TXCLK2 0x1118025c
+
+#endif // _nbio_6_1_SMN_HEADER
+
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
new file mode 100644
index 000000000000..5563f0715896
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _nbio_7_0_SMN_HEADER
+#define _nbio_7_0_SMN_HEADER
+
+
+#define smnCPM_CONTROL 0x11180460
+#define smnPCIE_CNTL2 0x11180070
+
+#define smnPCIE_PERF_COUNT_CNTL 0x11180200
+#define smnPCIE_PERF_CNTL_TXCLK 0x11180204
+#define smnPCIE_PERF_COUNT0_TXCLK 0x11180208
+#define smnPCIE_PERF_COUNT1_TXCLK 0x1118020c
+#define smnPCIE_PERF_CNTL_MST_R_CLK 0x11180210
+#define smnPCIE_PERF_COUNT0_MST_R_CLK 0x11180214
+#define smnPCIE_PERF_COUNT1_MST_R_CLK 0x11180218
+#define smnPCIE_PERF_CNTL_MST_C_CLK 0x1118021c
+#define smnPCIE_PERF_COUNT0_MST_C_CLK 0x11180220
+#define smnPCIE_PERF_COUNT1_MST_C_CLK 0x11180224
+#define smnPCIE_PERF_CNTL_SLV_R_CLK 0x11180228
+#define smnPCIE_PERF_COUNT0_SLV_R_CLK 0x1118022c
+#define smnPCIE_PERF_COUNT1_SLV_R_CLK 0x11180230
+#define smnPCIE_PERF_CNTL_SLV_S_C_CLK 0x11180234
+#define smnPCIE_PERF_COUNT0_SLV_S_C_CLK 0x11180238
+#define smnPCIE_PERF_COUNT1_SLV_S_C_CLK 0x1118023c
+#define smnPCIE_PERF_CNTL_SLV_NS_C_CLK 0x11180240
+#define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x11180244
+#define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x11180248
+#define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1118024c
+#define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x11180250
+#define smnPCIE_PERF_CNTL_TXCLK2 0x11180254
+#define smnPCIE_PERF_COUNT0_TXCLK2 0x11180258
+#define smnPCIE_PERF_COUNT1_TXCLK2 0x1118025c
+
+#endif // _nbio_7_0_SMN_HEADER
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
new file mode 100644
index 000000000000..c1457d880c4d
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _nbio_7_4_0_SMN_HEADER
+#define _nbio_7_4_0_SMN_HEADER
+
+
+#define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
+#define smnCPM_CONTROL 0x11180460
+#define smnPCIE_CNTL2 0x11180070
+#define smnPCIE_CI_CNTL 0x11180080
+
+#define smnPCIE_PERF_COUNT_CNTL 0x11180200
+#define smnPCIE_PERF_CNTL_TXCLK1 0x11180204
+#define smnPCIE_PERF_COUNT0_TXCLK1 0x11180208
+#define smnPCIE_PERF_COUNT1_TXCLK1 0x1118020c
+#define smnPCIE_PERF_CNTL_TXCLK2 0x11180210
+#define smnPCIE_PERF_COUNT0_TXCLK2 0x11180214
+#define smnPCIE_PERF_COUNT1_TXCLK2 0x11180218
+#define smnPCIE_PERF_CNTL_TXCLK3 0x1118021c
+#define smnPCIE_PERF_COUNT0_TXCLK3 0x11180220
+#define smnPCIE_PERF_COUNT1_TXCLK3 0x11180224
+#define smnPCIE_PERF_CNTL_TXCLK4 0x11180228
+#define smnPCIE_PERF_COUNT0_TXCLK4 0x1118022c
+#define smnPCIE_PERF_COUNT1_TXCLK4 0x11180230
+#define smnPCIE_PERF_CNTL_SCLK1 0x11180234
+#define smnPCIE_PERF_COUNT0_SCLK1 0x11180238
+#define smnPCIE_PERF_COUNT1_SCLK1 0x1118023c
+#define smnPCIE_PERF_CNTL_SCLK2 0x11180240
+#define smnPCIE_PERF_COUNT0_SCLK2 0x11180244
+#define smnPCIE_PERF_COUNT1_SCLK2 0x11180248
+#define smnPCIE_PERF_CNTL_EVENT_LC_PORT_SEL 0x1118024c
+#define smnPCIE_PERF_CNTL_EVENT_CI_PORT_SEL 0x11180250
+
+#endif // _nbio_7_4_0_SMN_HEADER
--
2.17.1
|
