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From 8e46fa965e989122a27d0c39ae2722a299269ab1 Mon Sep 17 00:00:00 2001
From: Flora Cui <flora.cui@amd.com>
Date: Sat, 10 Oct 2015 17:11:12 +0800
Subject: [PATCH 0140/2940] drm/amdgpu: [hybrid] add query for aperture va
range
Change-Id: I9021faca76e6ff060dbc02542d056eb424b75d15
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 17 +++++++++++++++++
include/uapi/drm/amdgpu_drm.h | 21 +++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 7d3d76a1a9dd..b5eaf39cd301 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -298,6 +298,23 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
flush_delayed_work(&adev->late_init_work);
switch (info->query) {
+ case AMDGPU_INFO_VIRTUAL_RANGE: {
+ struct drm_amdgpu_virtual_range range_info;
+ switch (info->virtual_range.aperture) {
+ case AMDGPU_SUA_APERTURE_PRIVATE:
+ range_info.start = adev->gmc.private_aperture_start;
+ range_info.end = adev->gmc.private_aperture_end;
+ break;
+ case AMDGPU_SUA_APERTURE_SHARED:
+ range_info.start = adev->gmc.shared_aperture_start;
+ range_info.end = adev->gmc.shared_aperture_end;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return copy_to_user(out, &range_info,
+ min((size_t)size, sizeof(range_info))) ? -EFAULT : 0;
+ }
case AMDGPU_INFO_ACCEL_WORKING:
ui32 = adev->accel_working;
return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index e879f38611a1..763874711532 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -722,6 +722,12 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
+/* Hybrid Stack Specific Defs*/
+/* gpu capability */
+#define AMDGPU_INFO_CAPABILITY 0x50
+/* virtual range */
+#define AMDGPU_INFO_VIRTUAL_RANGE 0x51
+
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
@@ -778,6 +784,11 @@ struct drm_amdgpu_info {
__u32 flags;
} read_mmr_reg;
+ struct {
+ uint32_t aperture;
+ uint32_t _pad;
+ } virtual_range;
+
struct drm_amdgpu_query_fw query_fw;
struct {
@@ -992,6 +1003,16 @@ struct drm_amdgpu_info_vce_clock_table {
#define AMDGPU_FAMILY_AI 141 /* Vega10 */
#define AMDGPU_FAMILY_RV 142 /* Raven */
+/**
+ * Definition of System Unified Address (SUA) apertures
+ */
+#define AMDGPU_SUA_APERTURE_PRIVATE 1
+#define AMDGPU_SUA_APERTURE_SHARED 2
+struct drm_amdgpu_virtual_range {
+ uint64_t start;
+ uint64_t end;
+};
+
/*
* Definition of free sync enter and exit signals
* We may have more options in the future
--
2.17.1
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