blob: 97438bedb7bfaae16bdf6d61147830b97dda9390 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
|
From 19543456a9456590ee830122b4a5b7fb3e9901ae Mon Sep 17 00:00:00 2001
From: Hawking Zhang <Hawking.Zhang@amd.com>
Date: Mon, 19 Mar 2018 17:28:28 +0800
Subject: [PATCH 3823/4131] drm/amdgpu/nbio6: Correct PCIE_INDEX/DATA pair used
for smn register accessing
PCIE_INDEX2/DATA2 pair will be used for smn register accessing since from vega.
PCIE_INDEX/DATA pair should be reserved for smu
Change-Id: Ie597d89001e706225521c94161d2b40443ec3c48
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 1cf3424..6f9c549 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -220,12 +220,12 @@ static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev)
{
- return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX);
+ return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
}
static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)
{
- return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA);
+ return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
}
static const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
--
2.7.4
|
