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From b987c509f6d35622197065214da1ddec2710a8cb Mon Sep 17 00:00:00 2001
From: Flora Cui <flora.cui@amd.com>
Date: Fri, 8 Dec 2017 23:08:40 -0500
Subject: [PATCH 3471/4131] drm/amdgpu: add amdgpu interface to query cu info
Signed-off-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 17 ++++-------------
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 19 +++++--------------
2 files changed, 9 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index aeeced9..916ab66 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -5251,19 +5251,10 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
cu_info->number = active_cu_number;
cu_info->ao_cu_mask = ao_cu_mask;
cu_info->simd_per_cu = NUM_SIMD_PER_CU;
- switch (adev->asic_type) {
- case CHIP_KAVERI:
- case CHIP_HAWAII:
- cu_info->max_waves_per_simd = 10;
- cu_info->max_scratch_slots_per_cu = 32;
- cu_info->wave_front_size = 64;
- cu_info->lds_size = 64;
- break;
- default:
- dev_warn(adev->dev, "CU info asic_type [0x%x] not supported\n",
- adev->asic_type);
- break;
- }
+ cu_info->max_waves_per_simd = 10;
+ cu_info->max_scratch_slots_per_cu = 32;
+ cu_info->wave_front_size = 64;
+ cu_info->lds_size = 64;
}
const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 918cefc..70dc123 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -7116,20 +7116,11 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev)
cu_info->number = active_cu_number;
cu_info->ao_cu_mask = ao_cu_mask;
cu_info->simd_per_cu = NUM_SIMD_PER_CU;
- switch (adev->asic_type) {
- case CHIP_TONGA:
- case CHIP_CARRIZO:
- case CHIP_POLARIS10:
- case CHIP_POLARIS11:
- cu_info->max_waves_per_simd = 10;
- cu_info->max_scratch_slots_per_cu = 32;
- cu_info->wave_front_size = 64;
- cu_info->lds_size = 64;
- break;
- default:
- dev_warn(adev->dev, "CU info asic_type [0x%x] not supported\n",
- adev->asic_type);
- }
+ cu_info->max_waves_per_simd = 10;
+ cu_info->max_scratch_slots_per_cu = 32;
+ cu_info->wave_front_size = 64;
+ cu_info->lds_size = 64;
+
}
const struct amdgpu_ip_block_version gfx_v8_0_ip_block =
--
2.7.4
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