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From 2c95bcf9cb7df34b6a8eff497aaca27597e12511 Mon Sep 17 00:00:00 2001
From: Rex Zhu <Rex.Zhu@amd.com>
Date: Fri, 20 Apr 2018 13:03:15 +0800
Subject: [PATCH 3337/4131] drm/amd/pp: Use dynamic gfx_clk rather than
hardcoded values
fix bug SWDEV-150537:
RGP tool: Reported profiling clocks in RGP is not as expected
Change-Id: I477e90c053ab775bdef110cca88a8961cb5723d1
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 44 ++++++++++++++++----------
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h | 2 --
2 files changed, 27 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
index 6feeff8..0cb4c32 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
@@ -396,7 +396,7 @@ static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
&result),
"Attempt to get min GFXCLK Failed!",
return -1);
- rv_data->gfx_min_freq_limit = result * 100;
+ rv_data->gfx_min_freq_limit = result / 10 * 1000;
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetMaxGfxclkFrequency),
@@ -406,7 +406,7 @@ static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
&result),
"Attempt to get max GFXCLK Failed!",
return -1);
- rv_data->gfx_max_freq_limit = result * 100;
+ rv_data->gfx_max_freq_limit = result / 10 * 1000;
return 0;
}
@@ -488,6 +488,7 @@ static int rv_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
enum amd_dpm_forced_level level)
{
+ struct rv_hwmgr *data = hwmgr->backend;
if (hwmgr->smu_version < 0x1E3700) {
pr_info("smu firmware version too old, can not set dpm level\n");
return 0;
@@ -498,7 +499,7 @@ static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinGfxClk,
- RAVEN_UMD_PSTATE_PEAK_GFXCLK);
+ data->gfx_max_freq_limit/100);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinFclkByFreq,
RAVEN_UMD_PSTATE_PEAK_FCLK);
@@ -511,7 +512,7 @@ static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxGfxClk,
- RAVEN_UMD_PSTATE_PEAK_GFXCLK);
+ data->gfx_max_freq_limit/100);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxFclkByFreq,
RAVEN_UMD_PSTATE_PEAK_FCLK);
@@ -525,10 +526,10 @@ static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinGfxClk,
- RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ data->gfx_min_freq_limit/100);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxGfxClk,
- RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ data->gfx_min_freq_limit/100);
break;
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
smum_send_msg_to_smc_with_parameter(hwmgr,
@@ -568,7 +569,7 @@ static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
case AMD_DPM_FORCED_LEVEL_AUTO:
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinGfxClk,
- RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ data->gfx_min_freq_limit/100);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinFclkByFreq,
RAVEN_UMD_PSTATE_MIN_FCLK);
@@ -581,7 +582,7 @@ static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxGfxClk,
- RAVEN_UMD_PSTATE_PEAK_GFXCLK);
+ data->gfx_max_freq_limit/100);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxFclkByFreq,
RAVEN_UMD_PSTATE_PEAK_FCLK);
@@ -595,10 +596,10 @@ static int rv_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
case AMD_DPM_FORCED_LEVEL_LOW:
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinGfxClk,
- RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ data->gfx_min_freq_limit/100);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMaxGfxClk,
- RAVEN_UMD_PSTATE_MIN_GFXCLK);
+ data->gfx_min_freq_limit/100);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetHardMinFclkByFreq,
RAVEN_UMD_PSTATE_MIN_FCLK);
@@ -736,7 +737,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
struct rv_hwmgr *data = (struct rv_hwmgr *)(hwmgr->backend);
struct rv_voltage_dependency_table *mclk_table =
data->clock_vol_info.vdd_dep_on_fclk;
- int i, now, size = 0;
+ uint32_t i, now, size = 0;
switch (type) {
case PP_SCLK:
@@ -749,14 +750,23 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
"Attempt to get current GFXCLK Failed!",
return -1);
+ /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
+ if (now == data->gfx_max_freq_limit/100)
+ i = 2;
+ else if (now == data->gfx_min_freq_limit/100)
+ i = 0;
+ else
+ i = 1;
+
size += sprintf(buf + size, "0: %uMhz %s\n",
- data->gfx_min_freq_limit / 100,
- ((data->gfx_min_freq_limit / 100)
- == now) ? "*" : "");
+ data->gfx_min_freq_limit/100,
+ i == 0 ? "*" : "");
size += sprintf(buf + size, "1: %uMhz %s\n",
- data->gfx_max_freq_limit / 100,
- ((data->gfx_max_freq_limit / 100)
- == now) ? "*" : "");
+ i == 1 ? now : RAVEN_UMD_PSTATE_GFXCLK,
+ i == 1 ? "*" : "");
+ size += sprintf(buf + size, "2: %uMhz %s\n",
+ data->gfx_max_freq_limit/100,
+ i == 2 ? "*" : "");
break;
case PP_MCLK:
PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
index c3bc311..29afa5c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.h
@@ -310,11 +310,9 @@ int rv_init_function_pointers(struct pp_hwmgr *hwmgr);
#define RAVEN_UMD_PSTATE_FCLK 933
#define RAVEN_UMD_PSTATE_VCE 0x03C00320
-#define RAVEN_UMD_PSTATE_PEAK_GFXCLK 1100
#define RAVEN_UMD_PSTATE_PEAK_SOCCLK 757
#define RAVEN_UMD_PSTATE_PEAK_FCLK 1200
-#define RAVEN_UMD_PSTATE_MIN_GFXCLK 200
#define RAVEN_UMD_PSTATE_MIN_FCLK 400
#define RAVEN_UMD_PSTATE_MIN_SOCCLK 200
#define RAVEN_UMD_PSTATE_MIN_VCE 0x0190012C
--
2.7.4
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