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From b8d075a566d536076953dd6102e5ac190f09f21e Mon Sep 17 00:00:00 2001
From: Rex Zhu <Rex.Zhu@amd.com>
Date: Mon, 8 Jan 2018 16:50:59 +0800
Subject: [PATCH 3161/4131] drm/amd/pp: Add memory clock info display on Cz/St
show mclk info as in MHz on Cz/St as
0: 333Mhz *
1: 800Mhz
Change-Id: I2f29c43601c1b9cabea9088f076e28dc44428ce4
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 0b8aa44..e574af1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1582,6 +1582,7 @@ static int cz_force_clock_level(struct pp_hwmgr *hwmgr,
static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
enum pp_clock_type type, char *buf)
{
+ struct cz_hwmgr *data = (struct cz_hwmgr *)(hwmgr->backend);
struct phm_clock_voltage_dependency_table *sclk_table =
hwmgr->dyn_state.vddc_dependency_on_sclk;
int i, now, size = 0;
@@ -1599,6 +1600,18 @@ static int cz_print_clock_levels(struct pp_hwmgr *hwmgr,
i, sclk_table->entries[i].clk / 100,
(i == now) ? "*" : "");
break;
+ case PP_MCLK:
+ now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
+ CGS_IND_REG__SMC,
+ ixTARGET_AND_CURRENT_PROFILE_INDEX),
+ TARGET_AND_CURRENT_PROFILE_INDEX,
+ CURR_MCLK_INDEX);
+
+ for (i = CZ_NUM_NBPMEMORYCLOCK; i > 0; i--)
+ size += sprintf(buf + size, "%d: %uMhz %s\n",
+ CZ_NUM_NBPMEMORYCLOCK-i, data->sys_info.nbp_memory_clock[i-1] / 100,
+ (CZ_NUM_NBPMEMORYCLOCK-i == now) ? "*" : "");
+ break;
default:
break;
}
--
2.7.4
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