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From 1ad82c0fa47a131fdea2b8eaafbf49fd46e0a467 Mon Sep 17 00:00:00 2001
From: Tony Cheng <tony.cheng@amd.com>
Date: Wed, 22 Nov 2017 11:51:30 -0500
Subject: [PATCH 2914/4131] drm/amd/display: really fix time out in init
sequence
REG_UPDATE_2 return the reg value it write out through MMIO
we need to do a REG_READ to confirm the value is written out
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 1984ac2..2d843b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -42,13 +42,14 @@ void hubp1_set_blank(struct hubp *hubp, bool blank)
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
uint32_t blank_en = blank ? 1 : 0;
- uint32_t reg_val = 0;
- reg_val = REG_UPDATE_2(DCHUBP_CNTL,
+ REG_UPDATE_2(DCHUBP_CNTL,
HUBP_BLANK_EN, blank_en,
HUBP_TTU_DISABLE, blank_en);
if (blank) {
+ uint32_t reg_val = REG_READ(DCHUBP_CNTL);
+
if (reg_val) {
/* init sequence workaround: in case HUBP is
* power gated, this wait would timeout.
--
2.7.4
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