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From 9ac1153255cffbfd853864bbfcb3d7786fb324fa Mon Sep 17 00:00:00 2001
From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Date: Tue, 31 Oct 2017 18:05:31 -0400
Subject: [PATCH 2723/4131] drm/amd/display: remove unnecessary waits in dcn10
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 9 ---------
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 13 +------------
.../gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 13 ++-----------
3 files changed, 3 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 5250615..3b0db25 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -140,10 +140,6 @@
BL_REG_LIST()
#define HWSEQ_DCN_REG_LIST()\
- SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 0), \
- SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 1), \
- SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 2), \
- SRII(OTG_GLOBAL_SYNC_STATUS, OTG, 3), \
SRII(DCHUBP_CNTL, HUBP, 0), \
SRII(DCHUBP_CNTL, HUBP, 1), \
SRII(DCHUBP_CNTL, HUBP, 2), \
@@ -264,7 +260,6 @@ struct dce_hwseq_registers {
uint32_t DCHUB_AGP_BOT;
uint32_t DCHUB_AGP_TOP;
- uint32_t OTG_GLOBAL_SYNC_STATUS[4];
uint32_t DCHUBP_CNTL[4];
uint32_t HUBP_CLK_CNTL[4];
uint32_t DPP_CONTROL[4];
@@ -438,8 +433,6 @@ struct dce_hwseq_registers {
#define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\
HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\
HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \
- HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR, mask_sh), \
- HWS_SF(OTG0_, OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_OCCURRED, mask_sh), \
HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \
HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \
HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
@@ -536,8 +529,6 @@ struct dce_hwseq_registers {
type LVTMA_PWRSEQ_TARGET_STATE_R;
#define HWSEQ_DCN_REG_FIELD_LIST(type) \
- type VUPDATE_NO_LOCK_EVENT_CLEAR; \
- type VUPDATE_NO_LOCK_EVENT_OCCURRED; \
type HUBP_VTG_SEL; \
type HUBP_CLOCK_ENABLE; \
type DPP_CLOCK_ENABLE; \
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 617c02a..7ff79ef 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -565,8 +565,6 @@ static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
struct mpc *mpc = dc->res_pool->mpc;
int opp_id, z_idx;
int mpcc_id = -1;
- struct timing_generator *tg = pipe_ctx->stream_res.tg;
- struct dce_hwseq *hws = dc->hwseq;
/* look at tree rather than mi here to know if we already reset */
for (opp_id = 0; opp_id < dc->res_pool->pipe_count; opp_id++) {
@@ -586,7 +584,7 @@ static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
return;
mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree),
- dc->res_pool->opps[opp_id]->inst, fe_idx);
+ dc->res_pool->opps[opp_id]->inst, fe_idx);
if (hubp->funcs->hubp_disconnect)
hubp->funcs->hubp_disconnect(hubp);
@@ -607,10 +605,6 @@ static void plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
pipe_ctx->bottom_pipe = NULL;
}
pipe_ctx->plane_state = NULL;
-
- /* TODO: Move to tg. */
- REG_UPDATE(OTG_GLOBAL_SYNC_STATUS[tg->inst],
- VUPDATE_NO_LOCK_EVENT_CLEAR, 1);
}
/* disable HW used by plane.
@@ -630,11 +624,6 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
if (opp_id == 0xf)
return;
- if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
- REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst],
- VUPDATE_NO_LOCK_EVENT_OCCURRED, 1,
- 1, 100000);
-
mpc->funcs->wait_for_idle(mpc, hubp->mpcc_id);
dc->res_pool->opps[hubp->opp_id]->mpcc_disconnect_pending[hubp->mpcc_id] = false;
/*dm_logger_write(dc->ctx->logger, LOG_ERROR,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 819c4ed..90e94a3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -393,19 +393,9 @@ static void tgn10_enable_optc_clock(struct timing_generator *tg, bool enable)
OTG_CLOCK_GATE_DIS, 0,
OTG_CLOCK_EN, 0);
- if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
- REG_WAIT(OTG_CLOCK_CONTROL,
- OTG_CLOCK_ON, 0,
- 1, 1000);
-
REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
OPTC_INPUT_CLK_GATE_DIS, 0,
OPTC_INPUT_CLK_EN, 0);
-
- if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
- REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
- OPTC_INPUT_CLK_ON, 0,
- 1, 1000);
}
}
@@ -568,10 +558,11 @@ static void tgn10_lock(struct timing_generator *tg)
REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
OTG_MASTER_UPDATE_LOCK, 1);
+ /* Should be fast, status does not update on maximus */
if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
REG_WAIT(OTG_MASTER_UPDATE_LOCK,
UPDATE_LOCK_STATUS, 1,
- 1, 100);
+ 1, 10);
}
static void tgn10_unlock(struct timing_generator *tg)
--
2.7.4
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