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From f8c86a5596d29d98ad50a5be0d40d17e124a84fd Mon Sep 17 00:00:00 2001
From: Tony Cheng <tony.cheng@amd.com>
Date: Wed, 27 Sep 2017 09:20:51 -0400
Subject: [PATCH 2508/4131] drm/amd/display: align DCLK to voltage level
in past program SMU will use all voltage headroom. RV does not
if DAL need higher voltage for DCFCLK or DISPCLK, also increase FCLK
to improve stutter as voltage is already
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4 ++++
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 +
3 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index cf474eb..9337cca 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1049,6 +1049,10 @@ bool dcn_validate_bandwidth(
else
bw_consumed = v->fabric_and_dram_bandwidth_vmax0p9;
+ if (bw_consumed < v->fabric_and_dram_bandwidth)
+ if (dc->debug.voltage_align_fclk)
+ bw_consumed = v->fabric_and_dram_bandwidth;
+
display_pipe_configuration(v);
calc_wm_sets_and_perf_params(context, v);
context->bw.dcn.calc_clk.fclk_khz = (int)(bw_consumed * 1000000 /
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index cf59626..349d3da 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -188,6 +188,7 @@ struct dc_debug {
enum dcc_option disable_dcc;
enum pipe_split_policy pipe_split_policy;
bool force_single_disp_pipe_split;
+ bool voltage_align_fclk;
bool disable_dfs_bypass;
bool disable_dpp_power_gate;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index 6751b6e..7a766be 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -428,6 +428,7 @@ static const struct dc_debug debug_defaults_drv = {
.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
.disable_dcc = DCC_ENABLE,
+ .voltage_align_fclk = true,
};
static const struct dc_debug debug_defaults_diags = {
--
2.7.4
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