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From 6c1edb07b1df1854401bad2623d01f67c41d4b0a Mon Sep 17 00:00:00 2001
From: Wenjing Liu <Wenjing.Liu@amd.com>
Date: Wed, 23 Aug 2017 17:02:34 -0400
Subject: [PATCH 2322/4131] drm/amd/display: do not reset lane count in EQ
fallback
[Description]
According to DP1.4 specs we should not reset lane count back
when falling back in failing EQ training.
This causes PHY test pattern compliance to fail as infinite LT
when LT fails EQ to 4 RBR and fails CR in a loop.
Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index e19447d..446e293 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1302,8 +1302,6 @@ bool decide_fallback_link_setting(
current_link_setting->lane_count);
} else if (!reached_minimum_link_rate
(current_link_setting->link_rate)) {
- current_link_setting->lane_count =
- initial_link_settings.lane_count;
current_link_setting->link_rate =
reduce_link_rate(
current_link_setting->link_rate);
--
2.7.4
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