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From 51e17f94b131b19726d3709bb58eefa212fd7d6b Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@amd.com>
Date: Mon, 13 Nov 2017 15:45:31 -0500
Subject: [PATCH 2182/4131] drm/amdgpu/gfx7: use cached values for raster
config in clear state
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Use the cached values rather than hardcoding it.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 25 ++-----------------------
1 file changed, 2 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index d78d1da..c32257d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2553,29 +2553,8 @@ static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
- switch (adev->asic_type) {
- case CHIP_BONAIRE:
- amdgpu_ring_write(ring, 0x16000012);
- amdgpu_ring_write(ring, 0x00000000);
- break;
- case CHIP_KAVERI:
- amdgpu_ring_write(ring, 0x00000000); /* XXX */
- amdgpu_ring_write(ring, 0x00000000);
- break;
- case CHIP_KABINI:
- case CHIP_MULLINS:
- amdgpu_ring_write(ring, 0x00000000); /* XXX */
- amdgpu_ring_write(ring, 0x00000000);
- break;
- case CHIP_HAWAII:
- amdgpu_ring_write(ring, 0x3a00161a);
- amdgpu_ring_write(ring, 0x0000002e);
- break;
- default:
- amdgpu_ring_write(ring, 0x00000000);
- amdgpu_ring_write(ring, 0x00000000);
- break;
- }
+ amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
+ amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
--
2.7.4
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