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From 74be585a3f3ed1d8fe291921df5093bc0e8a0a4e Mon Sep 17 00:00:00 2001
From: Jay Cornwall <Jay.Cornwall@amd.com>
Date: Fri, 30 Jun 2017 12:53:25 -0500
Subject: [PATCH 1730/4131] drm/amdkfd: Initialize gfx9 workgroup state offset
to control stack size
MEC microcode resets CP_HQD_WG_STATE_OFFSET to CP_HQD_CNTL_STACK_SIZE
after a restore event. Although this could be zero on gfx9, since the
control stack is not stored at the beginning of the context save area,
hardware block testing is still done with this configuration
Align MQD initialization of CP_HQD_WG_STATE_OFFSET with CP expectation
by initializing to CP_HQD_CNTL_STACK_SIZE.
Change-Id: I28ee578c1242a6de56bb28ae84469d70ab6dfcb8
Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
---
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
index 1e956ff..3b1c231 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
@@ -167,7 +167,7 @@ static int init_mqd(struct mqd_manager *mm, void **mqd,
m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
- m->cp_hqd_wg_state_offset = 0;
+ m->cp_hqd_wg_state_offset = q->ctl_stack_size;
}
*mqd = m;
@@ -307,7 +307,8 @@ static int get_wave_state(struct mqd_manager *mm, void *mqd,
*ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
m->cp_hqd_cntl_stack_offset;
- *save_area_used_size = m->cp_hqd_wg_state_offset;
+ *save_area_used_size = m->cp_hqd_wg_state_offset -
+ m->cp_hqd_cntl_stack_size;
if (copy_to_user(ctl_stack, mqd_ctl_stack, m->cp_hqd_cntl_stack_size))
return -EFAULT;
--
2.7.4
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