blob: dac4f174577e9f9434f89d4098f8bf85ca885937 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
|
From 4ff475bd08166f2eefcd112c46cb94ba2551446a Mon Sep 17 00:00:00 2001
From: Flora Cui <Flora.Cui@amd.com>
Date: Fri, 9 Sep 2016 14:19:10 +0800
Subject: [PATCH 0772/4131] drm/amdgpu: fix gart flag calc in dgma
use the general routine to cacl gart flag
Change-Id: I053ece5070e86bb7d2b700bd1b4f5c031af6d5c4
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 4b23cc7..5eca07c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -359,9 +359,7 @@ int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data,
for (i = 0; i < abo->tbo.num_pages; i++)
dma_addr[i] = args->addr + i * PAGE_SIZE;
- flags = AMDGPU_PTE_VALID | AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE;
- if (adev->asic_type >= CHIP_TONGA)
- flags |= AMDGPU_PTE_EXECUTABLE;
+ flags = amdgpu_ttm_tt_pte_flags(adev, abo->tbo.ttm, &abo->tbo.mem);
offset = amdgpu_bo_gpu_offset(abo);
offset -= adev->mman.bdev.man[TTM_PL_TT].gpu_offset;
--
2.7.4
|
