diff options
Diffstat (limited to 'meta-snowyowl')
41 files changed, 3386 insertions, 0 deletions
diff --git a/meta-snowyowl/recipes-kernel/linux/files/0165-License-cleanup-add-SPDX-GPL-2.0-license-identifier-.patch b/meta-snowyowl/recipes-kernel/linux/files/0165-License-cleanup-add-SPDX-GPL-2.0-license-identifier-.patch new file mode 100644 index 00000000..2c2e70e7 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0165-License-cleanup-add-SPDX-GPL-2.0-license-identifier-.patch @@ -0,0 +1,179 @@ +From 574c9f1f7a89d3f9179d3c4500223d0fee962153 Mon Sep 17 00:00:00 2001 +From: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Date: Wed, 1 Nov 2017 15:07:57 +0100 +Subject: [PATCH 2/9] License cleanup: add SPDX GPL-2.0 license identifier to + files with no license + +Many source files in the tree are missing licensing information, which +makes it harder for compliance tools to determine the correct license. + +By default all files without license information are under the default +license of the kernel, which is GPL version 2. + +Update the files which contain no license information with the 'GPL-2.0' +SPDX license identifier. The SPDX identifier is a legally binding +shorthand, which can be used instead of the full boiler plate text. + +This patch is based on work done by Thomas Gleixner and Kate Stewart and +Philippe Ombredanne. + +How this work was done: + +Patches were generated and checked against linux-4.14-rc6 for a subset of +the use cases: + - file had no licensing information it it. + - file was a */uapi/* one with no licensing information in it, + - file was a */uapi/* one with existing licensing information, + +Further patches will be generated in subsequent months to fix up cases +where non-standard license headers were used, and references to license +had to be inferred by heuristics based on keywords. + +The analysis to determine which SPDX License Identifier to be applied to +a file was done in a spreadsheet of side by side results from of the +output of two independent scanners (ScanCode & Windriver) producing SPDX +tag:value files created by Philippe Ombredanne. Philippe prepared the +base worksheet, and did an initial spot review of a few 1000 files. + +The 4.13 kernel was the starting point of the analysis with 60,537 files +assessed. Kate Stewart did a file by file comparison of the scanner +results in the spreadsheet to determine which SPDX license identifier(s) +to be applied to the file. She confirmed any determination that was not +immediately clear with lawyers working with the Linux Foundation. + +Criteria used to select files for SPDX license identifier tagging was: + - Files considered eligible had to be source code files. + - Make and config files were included as candidates if they contained >5 + lines of source + - File already had some variant of a license header in it (even if <5 + lines). + +All documentation files were explicitly excluded. + +The following heuristics were used to determine which SPDX license +identifiers to apply. + + - when both scanners couldn't find any license traces, file was + considered to have no license information in it, and the top level + COPYING file license applied. + + For non */uapi/* files that summary was: + + SPDX license identifier # files + ---------------------------------------------------|------- + GPL-2.0 11139 + + and resulted in the first patch in this series. + + If that file was a */uapi/* path one, it was "GPL-2.0 WITH + Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: + + SPDX license identifier # files + ---------------------------------------------------|------- + GPL-2.0 WITH Linux-syscall-note 930 + + and resulted in the second patch in this series. + + - if a file had some form of licensing information in it, and was one + of the */uapi/* ones, it was denoted with the Linux-syscall-note if + any GPL family license was found in the file or had no licensing in + it (per prior point). Results summary: + + SPDX license identifier # files + ---------------------------------------------------|------ + GPL-2.0 WITH Linux-syscall-note 270 + GPL-2.0+ WITH Linux-syscall-note 169 + ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 + ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 + LGPL-2.1+ WITH Linux-syscall-note 15 + GPL-1.0+ WITH Linux-syscall-note 14 + ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 + LGPL-2.0+ WITH Linux-syscall-note 4 + LGPL-2.1 WITH Linux-syscall-note 3 + ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 + ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 + + and that resulted in the third patch in this series. + + - when the two scanners agreed on the detected license(s), that became + the concluded license(s). + + - when there was disagreement between the two scanners (one detected a + license but the other didn't, or they both detected different + licenses) a manual inspection of the file occurred. + + - In most cases a manual inspection of the information in the file + resulted in a clear resolution of the license that should apply (and + which scanner probably needed to revisit its heuristics). + + - When it was not immediately clear, the license identifier was + confirmed with lawyers working with the Linux Foundation. + + - If there was any question as to the appropriate license identifier, + the file was flagged for further research and to be revisited later + in time. + +In total, over 70 hours of logged manual review was done on the +spreadsheet to determine the SPDX license identifiers to apply to the +source files by Kate, Philippe, Thomas and, in some cases, confirmation +by lawyers working with the Linux Foundation. + +Kate also obtained a third independent scan of the 4.13 code base from +FOSSology, and compared selected files where the other two scanners +disagreed against that SPDX file, to see if there was new insights. The +Windriver scanner is based on an older version of FOSSology in part, so +they are related. + +Thomas did random spot checks in about 500 files from the spreadsheets +for the uapi headers and agreed with SPDX license identifier in the +files he inspected. For the non-uapi files Thomas did random spot checks +in about 15000 files. + +In initial set of patches against 4.14-rc6, 3 files were found to have +copy/paste license identifier errors, and have been fixed to reflect the +correct identifier. + +Additionally Philippe spent 10 hours this week doing a detailed manual +inspection and review of the 12,461 patched files from the initial patch +version early this week with: + - a full scancode scan run, collecting the matched texts, detected + license ids and scores + - reviewing anything where there was a license detected (about 500+ + files) to ensure that the applied SPDX license was correct + - reviewing anything where there was no detection but the patch license + was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied + SPDX license was correct + +This produced a worksheet with 20 files needing minor correction. This +worksheet was then exported into 3 different .csv files for the +different types of files to be modified. + +These .csv files were then reviewed by Greg. Thomas wrote a script to +parse the csv files and add the proper SPDX tag to the file, in the +format that the file expected. This script was further refined by Greg +based on the output to detect more types of files automatically and to +distinguish between header and source .c files (which need different +comment types.) Finally Greg ran the script using the .csv files to +generate the patches. + +Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> +Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> +Reviewed-by: Thomas Gleixner <tglx@linutronix.de> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/Makefile | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/net/ethernet/amd/xgbe/Makefile b/drivers/net/ethernet/amd/xgbe/Makefile +index 0dea8f5..620785f 100755 +--- a/drivers/net/ethernet/amd/xgbe/Makefile ++++ b/drivers/net/ethernet/amd/xgbe/Makefile +@@ -1,3 +1,4 @@ ++# SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_AMD_XGBE) += amd-xgbe.o + + amd-xgbe-objs := xgbe-main.o xgbe-drv.o xgbe-dev.o \ +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0166-mm-remove-__GFP_COLD.patch b/meta-snowyowl/recipes-kernel/linux/files/0166-mm-remove-__GFP_COLD.patch new file mode 100644 index 00000000..9a4c674a --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0166-mm-remove-__GFP_COLD.patch @@ -0,0 +1,58 @@ +From bfe5cf0c74a52b490e713d81fb60d3467a8dea30 Mon Sep 17 00:00:00 2001 +From: Mel Gorman <mgorman@techsingularity.net> +Date: Wed, 15 Nov 2017 17:38:03 -0800 +Subject: [PATCH 3/9] mm: remove __GFP_COLD + +As the page free path makes no distinction between cache hot and cold +pages, there is no real useful ordering of pages in the free list that +allocation requests can take advantage of. Juding from the users of +__GFP_COLD, it is likely that a number of them are the result of copying +other sites instead of actually measuring the impact. Remove the +__GFP_COLD parameter which simplifies a number of paths in the page +allocator. + +This is potentially controversial but bear in mind that the size of the +per-cpu pagelists versus modern cache sizes means that the whole per-cpu +list can often fit in the L3 cache. Hence, there is only a potential +benefit for microbenchmarks that alloc/free pages in a tight loop. It's +even worse when THP is taken into account which has little or no chance +of getting a cache-hot page as the per-cpu list is bypassed and the +zeroing of multiple pages will thrash the cache anyway. + +The truncate microbenchmarks are not shown as this patch affects the +allocation path and not the free path. A page fault microbenchmark was +tested but it showed no sigificant difference which is not surprising +given that the __GFP_COLD branches are a miniscule percentage of the +fault path. + +Link: http://lkml.kernel.org/r/20171018075952.10627-9-mgorman@techsingularity.net +Signed-off-by: Mel Gorman <mgorman@techsingularity.net> +Acked-by: Vlastimil Babka <vbabka@suse.cz> +Cc: Andi Kleen <ak@linux.intel.com> +Cc: Dave Chinner <david@fromorbit.com> +Cc: Dave Hansen <dave.hansen@intel.com> +Cc: Jan Kara <jack@suse.cz> +Cc: Johannes Weiner <hannes@cmpxchg.org> +Signed-off-by: Andrew Morton <akpm@linux-foundation.org> +Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-desc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-desc.c b/drivers/net/ethernet/amd/xgbe/xgbe-desc.c +index 45d9230..cc1e4f8 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-desc.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-desc.c +@@ -295,7 +295,7 @@ static int xgbe_alloc_pages(struct xgbe_prv_data *pdata, + order = alloc_order; + + /* Try to obtain pages, decreasing order if necessary */ +- gfp = GFP_ATOMIC | __GFP_COLD | __GFP_COMP | __GFP_NOWARN; ++ gfp = GFP_ATOMIC | __GFP_COMP | __GFP_NOWARN; + while (order >= 0) { + pages = alloc_pages_node(node, gfp, order); + if (pages) +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0167-net-amd-xgbe-Get-rid-of-custom-hex_dump_to_buffer.patch b/meta-snowyowl/recipes-kernel/linux/files/0167-net-amd-xgbe-Get-rid-of-custom-hex_dump_to_buffer.patch new file mode 100644 index 00000000..35ba333f --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0167-net-amd-xgbe-Get-rid-of-custom-hex_dump_to_buffer.patch @@ -0,0 +1,67 @@ +From 52147ee16906c134c01a75cb72ab134c1bd98f89 Mon Sep 17 00:00:00 2001 +From: Andy Shevchenko <andriy.shevchenko@linux.intel.com> +Date: Tue, 19 Dec 2017 23:22:15 +0200 +Subject: [PATCH 4/9] net: amd-xgbe: Get rid of custom hex_dump_to_buffer() + +Get rid of yet another custom hex_dump_to_buffer(). + +The output is slightly changed, i.e. each byte followed by white space. + +Note, we don't use print_hex_dump() here since the original code uses +nedev_dbg(). + +Acked-by: Tom Lendacky <thomas.lendacky@amd.com> +Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-drv.c | 24 +++++++----------------- + 1 file changed, 7 insertions(+), 17 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +index 1cb532b..e6984ac 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +@@ -2930,9 +2930,8 @@ void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, + void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx) + { + struct ethhdr *eth = (struct ethhdr *)skb->data; +- unsigned char *buf = skb->data; + unsigned char buffer[128]; +- unsigned int i, j; ++ unsigned int i; + + netdev_dbg(netdev, "\n************** SKB dump ****************\n"); + +@@ -2943,22 +2942,13 @@ void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx) + netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source); + netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto)); + +- for (i = 0, j = 0; i < skb->len;) { +- j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx", +- buf[i++]); +- +- if ((i % 32) == 0) { +- netdev_dbg(netdev, " %#06x: %s\n", i - 32, buffer); +- j = 0; +- } else if ((i % 16) == 0) { +- buffer[j++] = ' '; +- buffer[j++] = ' '; +- } else if ((i % 4) == 0) { +- buffer[j++] = ' '; +- } ++ for (i = 0; i < skb->len; i += 32) { ++ unsigned int len = min(skb->len - i, 32U); ++ ++ hex_dump_to_buffer(&skb->data[i], len, 32, 1, ++ buffer, sizeof(buffer), false); ++ netdev_dbg(netdev, " %#06x: %s\n", i, buffer); + } +- if (i % 32) +- netdev_dbg(netdev, " %#06x: %s\n", i - (i % 32), buffer); + + netdev_dbg(netdev, "\n************** SKB dump ****************\n"); + } +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0168-net-amd-xgbe-fix-comparison-to-bitshift-when-dealing.patch b/meta-snowyowl/recipes-kernel/linux/files/0168-net-amd-xgbe-fix-comparison-to-bitshift-when-dealing.patch new file mode 100644 index 00000000..6aba56fd --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0168-net-amd-xgbe-fix-comparison-to-bitshift-when-dealing.patch @@ -0,0 +1,33 @@ +From 88ff6467a9863d680484ab0afcf400c45b47ba78 Mon Sep 17 00:00:00 2001 +From: Wolfram Sang <wsa+renesas@sang-engineering.com> +Date: Mon, 5 Feb 2018 21:10:01 +0100 +Subject: [PATCH 5/9] net: amd-xgbe: fix comparison to bitshift when dealing + with a mask + +Due to a typo, the mask was destroyed by a comparison instead of a bit +shift. + +Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> +Acked-by: Tom Lendacky <thomas.lendacky@amd.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-drv.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +index e6984ac..5d47b69 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +@@ -594,7 +594,7 @@ static void xgbe_isr_task(unsigned long data) + + reissue_mask = 1 << 0; + if (!pdata->per_channel_irq) +- reissue_mask |= 0xffff < 4; ++ reissue_mask |= 0xffff << 4; + + XP_IOWRITE(pdata, XP_INT_REISSUE_EN, reissue_mask); + } +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0169-amd-xgbe-Restore-PCI-interrupt-enablement-setting-on.patch b/meta-snowyowl/recipes-kernel/linux/files/0169-amd-xgbe-Restore-PCI-interrupt-enablement-setting-on.patch new file mode 100644 index 00000000..c4e099c4 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0169-amd-xgbe-Restore-PCI-interrupt-enablement-setting-on.patch @@ -0,0 +1,38 @@ +From 6be6051f2873b517d8eeb6c302930d44ebe295f1 Mon Sep 17 00:00:00 2001 +From: Tom Lendacky <thomas.lendacky@amd.com> +Date: Tue, 20 Feb 2018 15:22:05 -0600 +Subject: [PATCH 6/9] amd-xgbe: Restore PCI interrupt enablement setting on + resume + +After resuming from suspend, the PCI device support must re-enable the +interrupt setting so that interrupts are actually delivered. + +Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-pci.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c +index 464824b..82d1f41 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-pci.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-pci.c +@@ -426,12 +426,11 @@ static int xgbe_pci_resume(struct pci_dev *pdev) + struct net_device *netdev = pdata->netdev; + int ret = 0; + ++ XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); ++ + pdata->lpm_ctrl &= ~MDIO_CTRL1_LPOWER; + XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, pdata->lpm_ctrl); + +- /* Enable all interrupts in the hardware */ +- XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); +- + if (netif_running(netdev)) { + ret = xgbe_powerup(netdev, XGMAC_DRIVER_CONTEXT); + +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0170-ethernet-Use-octal-not-symbolic-permissions.patch b/meta-snowyowl/recipes-kernel/linux/files/0170-ethernet-Use-octal-not-symbolic-permissions.patch new file mode 100644 index 00000000..98031fc3 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0170-ethernet-Use-octal-not-symbolic-permissions.patch @@ -0,0 +1,69 @@ +From 46fa149f6cd1172c5a6c8299cc47ef949e085788 Mon Sep 17 00:00:00 2001 +From: Joe Perches <joe@perches.com> +Date: Fri, 23 Mar 2018 16:34:44 -0700 +Subject: [PATCH 7/9] ethernet: Use octal not symbolic permissions + +Prefer the direct use of octal for permissions. + +Done with checkpatch -f --types=SYMBOLIC_PERMS --fix-inplace +and some typing. + +Miscellanea: + +o Whitespace neatening around these conversions. + +Signed-off-by: Joe Perches <joe@perches.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-drv.c | 10 +++++----- + drivers/net/ethernet/amd/xgbe/xgbe-main.c | 2 +- + 2 files changed, 6 insertions(+), 6 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +index 5d47b69..6bd8f38 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +@@ -136,21 +136,21 @@ static unsigned int ecc_ded_period = 600; + + #ifdef CONFIG_AMD_XGBE_HAVE_ECC + /* Only expose the ECC parameters if supported */ +-module_param(ecc_sec_info_threshold, uint, S_IWUSR | S_IRUGO); ++module_param(ecc_sec_info_threshold, uint, 0644); + MODULE_PARM_DESC(ecc_sec_info_threshold, + " ECC corrected error informational threshold setting"); + +-module_param(ecc_sec_warn_threshold, uint, S_IWUSR | S_IRUGO); ++module_param(ecc_sec_warn_threshold, uint, 0644); + MODULE_PARM_DESC(ecc_sec_warn_threshold, + " ECC corrected error warning threshold setting"); + +-module_param(ecc_sec_period, uint, S_IWUSR | S_IRUGO); ++module_param(ecc_sec_period, uint, 0644); + MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)"); + +-module_param(ecc_ded_threshold, uint, S_IWUSR | S_IRUGO); ++module_param(ecc_ded_threshold, uint, 0644); + MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting"); + +-module_param(ecc_ded_period, uint, S_IWUSR | S_IRUGO); ++module_param(ecc_ded_period, uint, 0644); + MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)"); + #endif + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-main.c b/drivers/net/ethernet/amd/xgbe/xgbe-main.c +index d91fa59..795e556 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-main.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-main.c +@@ -131,7 +131,7 @@ MODULE_VERSION(XGBE_DRV_VERSION); + MODULE_DESCRIPTION(XGBE_DRV_DESC); + + static int debug = -1; +-module_param(debug, int, S_IWUSR | S_IRUGO); ++module_param(debug, int, 0644); + MODULE_PARM_DESC(debug, " Network interface message level setting"); + + static const u32 default_msg_level = (NETIF_MSG_LINK | NETIF_MSG_IFDOWN | +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0171-amd-xgbe-Only-use-the-SFP-supported-transceiver-sign.patch b/meta-snowyowl/recipes-kernel/linux/files/0171-amd-xgbe-Only-use-the-SFP-supported-transceiver-sign.patch new file mode 100644 index 00000000..f4761c30 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0171-amd-xgbe-Only-use-the-SFP-supported-transceiver-sign.patch @@ -0,0 +1,137 @@ +From 884f0679eda94d4cc39f4b85cfc2697e66d4773f Mon Sep 17 00:00:00 2001 +From: Tom Lendacky <thomas.lendacky@amd.com> +Date: Mon, 23 Apr 2018 11:43:34 -0500 +Subject: [PATCH 8/9] amd-xgbe: Only use the SFP supported transceiver signals + +The SFP eeprom indicates the transceiver signals (Rx LOS, Tx Fault, etc.) +that it supports. Update the driver to include checking the eeprom data +when deciding whether to use a transceiver signal. + +Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c | 71 ++++++++++++++++++++++------- + 1 file changed, 54 insertions(+), 17 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +index f68e920..23139cf 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +@@ -250,6 +250,10 @@ enum xgbe_sfp_speed { + #define XGBE_SFP_BASE_VENDOR_SN 4 + #define XGBE_SFP_BASE_VENDOR_SN_LEN 16 + ++#define XGBE_SFP_EXTD_OPT1 1 ++#define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1) ++#define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3) ++ + #define XGBE_SFP_EXTD_DIAG 28 + #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) + +@@ -329,6 +333,7 @@ struct xgbe_phy_data { + + unsigned int sfp_gpio_address; + unsigned int sfp_gpio_mask; ++ unsigned int sfp_gpio_inputs; + unsigned int sfp_gpio_rx_los; + unsigned int sfp_gpio_tx_fault; + unsigned int sfp_gpio_mod_absent; +@@ -983,6 +988,49 @@ static void xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata) + phy_data->sfp_phy_avail = 1; + } + ++static bool xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data) ++{ ++ u8 *sfp_extd = phy_data->sfp_eeprom.extd; ++ ++ if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS)) ++ return false; ++ ++ if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) ++ return false; ++ ++ if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los)) ++ return true; ++ ++ return false; ++} ++ ++static bool xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data) ++{ ++ u8 *sfp_extd = phy_data->sfp_eeprom.extd; ++ ++ if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT)) ++ return false; ++ ++ if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) ++ return false; ++ ++ if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault)) ++ return true; ++ ++ return false; ++} ++ ++static bool xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data) ++{ ++ if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) ++ return false; ++ ++ if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent)) ++ return true; ++ ++ return false; ++} ++ + static bool xgbe_phy_belfuse_parse_quirks(struct xgbe_prv_data *pdata) + { + struct xgbe_phy_data *phy_data = pdata->phy_data; +@@ -1028,6 +1076,10 @@ static void xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata) + if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) + return; + ++ /* Update transceiver signals (eeprom extd/options) */ ++ phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data); ++ phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data); ++ + if (xgbe_phy_sfp_parse_quirks(pdata)) + return; + +@@ -1193,7 +1245,6 @@ static int xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata) + static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata) + { + struct xgbe_phy_data *phy_data = pdata->phy_data; +- unsigned int gpio_input; + u8 gpio_reg, gpio_ports[2]; + int ret; + +@@ -1208,23 +1259,9 @@ static void xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata) + return; + } + +- gpio_input = (gpio_ports[1] << 8) | gpio_ports[0]; +- +- if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT) { +- /* No GPIO, just assume the module is present for now */ +- phy_data->sfp_mod_absent = 0; +- } else { +- if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent))) +- phy_data->sfp_mod_absent = 0; +- } +- +- if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS) && +- (gpio_input & (1 << phy_data->sfp_gpio_rx_los))) +- phy_data->sfp_rx_los = 1; ++ phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0]; + +- if (!(phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT) && +- (gpio_input & (1 << phy_data->sfp_gpio_tx_fault))) +- phy_data->sfp_tx_fault = 1; ++ phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data); + } + + static void xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata) +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0172-Modification-to-previous-commit-305f3ad05fec3a5f0d7b.patch b/meta-snowyowl/recipes-kernel/linux/files/0172-Modification-to-previous-commit-305f3ad05fec3a5f0d7b.patch new file mode 100644 index 00000000..70a98481 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0172-Modification-to-previous-commit-305f3ad05fec3a5f0d7b.patch @@ -0,0 +1,184 @@ +From 9ce3ea9ed41bd4ecab41d7c23c8a924deb047616 Mon Sep 17 00:00:00 2001 +From: Sudheesh Mavila <sudheesh.mavila@amd.com> +Date: Thu, 3 May 2018 11:52:34 +0530 +Subject: [PATCH 9/9] Modification to previous commit + 305f3ad05fec3a5f0d7b51857b4bc99f527db7a4 and commit + 41fb5f9d75199370d9b3adc05bf642b0b13e29d4 + + Based on upstream commit 4d945663a6a0acf3cbe45940503f2eb9584bfee7 and 96f4d430c507ed4856048c2dc9c1a2ea5b5e74e4 + amd-xgbe: Improve KR auto-negotiation and training + amd-xgbe: Add pre/post auto-negotiation phy hooks + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c | 20 +++++++++++++++----- + drivers/net/ethernet/amd/xgbe/xgbe-drv.c | 1 + + drivers/net/ethernet/amd/xgbe/xgbe-i2c.c | 1 + + drivers/net/ethernet/amd/xgbe/xgbe-main.c | 1 + + drivers/net/ethernet/amd/xgbe/xgbe-mdio.c | 1 + + drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c | 15 ++++++++++----- + drivers/net/ethernet/amd/xgbe/xgbe.h | 3 ++- + 7 files changed, 31 insertions(+), 11 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c b/drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c +index 79387b4..b911439 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c +@@ -519,11 +519,21 @@ void xgbe_debugfs_init(struct xgbe_prv_data *pdata) + "debugfs_create_file failed\n"); + } + +- pfile = debugfs_create_bool("cdr_track_early", 0600, +- pdata->xgbe_debugfs, +- &pdata->debugfs_cdr_track_early); +- if (!pfile) +- netdev_err(pdata->netdev, "debugfs_create_bool failed\n"); ++ if (pdata->vdata->an_cdr_workaround) { ++ pfile = debugfs_create_bool("an_cdr_workaround", 0600, ++ pdata->xgbe_debugfs, ++ &pdata->debugfs_an_cdr_workaround); ++ if (!pfile) ++ netdev_err(pdata->netdev, ++ "debugfs_create_bool failed\n"); ++ ++ pfile = debugfs_create_bool("an_cdr_track_early", 0600, ++ pdata->xgbe_debugfs, ++ &pdata->debugfs_an_cdr_track_early); ++ if (!pfile) ++ netdev_err(pdata->netdev, ++ "debugfs_create_bool failed\n"); ++ } + + kfree(buf); + } +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +index 6bd8f38..b70832e 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c +@@ -118,6 +118,7 @@ + #include <linux/spinlock.h> + #include <linux/tcp.h> + #include <linux/if_vlan.h> ++#include <linux/interrupt.h> + #include <net/busy_poll.h> + #include <linux/clk.h> + #include <linux/if_ether.h> +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-i2c.c b/drivers/net/ethernet/amd/xgbe/xgbe-i2c.c +index dc74341..4d9062d 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-i2c.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-i2c.c +@@ -115,6 +115,7 @@ + */ + + #include <linux/module.h> ++#include <linux/interrupt.h> + #include <linux/kmod.h> + #include <linux/delay.h> + #include <linux/completion.h> +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-main.c b/drivers/net/ethernet/amd/xgbe/xgbe-main.c +index 795e556..441d0973 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-main.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-main.c +@@ -349,6 +349,7 @@ int xgbe_config_netdev(struct xgbe_prv_data *pdata) + XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1); + + /* Call MDIO/PHY initialization routine */ ++ pdata->debugfs_an_cdr_workaround = pdata->vdata->an_cdr_workaround; + ret = pdata->phy_if.phy_init(pdata); + if (ret) + return ret; +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c +index a511e61..1b45cd7 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c +@@ -114,6 +114,7 @@ + * THE POSSIBILITY OF SUCH DAMAGE. + */ + ++#include <linux/interrupt.h> + #include <linux/module.h> + #include <linux/kmod.h> + #include <linux/mdio.h> +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +index 23139cf..aac8843 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-phy-v2.c +@@ -152,6 +152,9 @@ + #define XGBE_CDR_DELAY_INC 10000 + #define XGBE_CDR_DELAY_MAX 100000 + ++/* RRC frequency during link status check */ ++#define XGBE_RRC_FREQUENCY 10 ++ + enum xgbe_port_mode { + XGBE_PORT_MODE_RSVD = 0, + XGBE_PORT_MODE_BACKPLANE, +@@ -2407,7 +2410,7 @@ static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) + return 1; + + /* No link, attempt a receiver reset cycle */ +- if (phy_data->rrc_count++) { ++ if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) { + phy_data->rrc_count = 0; + xgbe_phy_rrc(pdata); + } +@@ -2719,7 +2722,7 @@ static void xgbe_phy_cdr_track(struct xgbe_prv_data *pdata) + { + struct xgbe_phy_data *phy_data = pdata->phy_data; + +- if (!pdata->vdata->an_cdr_workaround) ++ if (!pdata->debugfs_an_cdr_workaround) + return; + + if (!phy_data->phy_cdr_notrack) +@@ -2739,7 +2742,7 @@ static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata) + { + struct xgbe_phy_data *phy_data = pdata->phy_data; + +- if (!pdata->vdata->an_cdr_workaround) ++ if (!pdata->debugfs_an_cdr_workaround) + return; + + if (phy_data->phy_cdr_notrack) +@@ -2756,13 +2759,13 @@ static void xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata) + + static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata) + { +- if (!pdata->debugfs_cdr_track_early) ++ if (!pdata->debugfs_an_cdr_track_early) + xgbe_phy_cdr_track(pdata); + } + + static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata) + { +- if (pdata->debugfs_cdr_track_early) ++ if (pdata->debugfs_an_cdr_track_early) + xgbe_phy_cdr_track(pdata); + } + +@@ -2785,6 +2788,8 @@ static void xgbe_phy_an_post(struct xgbe_prv_data *pdata) + default: + if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX) + phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC; ++ else ++ phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT; + break; + } + break; +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h +index a9c197c..95d4b56 100755 +--- a/drivers/net/ethernet/amd/xgbe/xgbe.h ++++ b/drivers/net/ethernet/amd/xgbe/xgbe.h +@@ -1264,7 +1264,8 @@ struct xgbe_prv_data { + + unsigned int debugfs_xi2c_reg; + +- bool debugfs_cdr_track_early; ++ bool debugfs_an_cdr_workaround; ++ bool debugfs_an_cdr_track_early; + }; + + /* Function prototypes*/ +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0173-crypto-gcm-wait-for-crypto-op-not-signal-safe.patch b/meta-snowyowl/recipes-kernel/linux/files/0173-crypto-gcm-wait-for-crypto-op-not-signal-safe.patch new file mode 100755 index 00000000..b784e59e --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0173-crypto-gcm-wait-for-crypto-op-not-signal-safe.patch @@ -0,0 +1,43 @@ +From 49050074c6839e918b47394c39ccdd8d53959543 Mon Sep 17 00:00:00 2001 +From: Gilad Ben-Yossef <gilad@benyossef.com> +Date: Thu, 18 May 2017 16:29:25 +0300 +Subject: [PATCH 019/331] crypto: gcm - wait for crypto op not signal safe + +commit f3ad587070d6bd961ab942b3fd7a85d00dfc934b upstream. + +crypto_gcm_setkey() was using wait_for_completion_interruptible() to +wait for completion of async crypto op but if a signal occurs it +may return before DMA ops of HW crypto provider finish, thus +corrupting the data buffer that is kfree'ed in this case. + +Resolve this by using wait_for_completion() instead. + +Reported-by: Eric Biggers <ebiggers3@gmail.com> +Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + crypto/gcm.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/crypto/gcm.c b/crypto/gcm.c +index f624ac9..dd33fbd 100644 +--- a/crypto/gcm.c ++++ b/crypto/gcm.c +@@ -152,10 +152,8 @@ static int crypto_gcm_setkey(struct crypto_aead *aead, const u8 *key, + + err = crypto_skcipher_encrypt(&data->req); + if (err == -EINPROGRESS || err == -EBUSY) { +- err = wait_for_completion_interruptible( +- &data->result.completion); +- if (!err) +- err = data->result.err; ++ wait_for_completion(&data->result.completion); ++ err = data->result.err; + } + + if (err) +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0174-crypto-drbg-wait-for-crypto-op-not-signal-safe.patch b/meta-snowyowl/recipes-kernel/linux/files/0174-crypto-drbg-wait-for-crypto-op-not-signal-safe.patch new file mode 100755 index 00000000..232d5dd8 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0174-crypto-drbg-wait-for-crypto-op-not-signal-safe.patch @@ -0,0 +1,42 @@ +From 1b7a262b9e41217cd8fe0c4b0bf7532e4ed5d4bb Mon Sep 17 00:00:00 2001 +From: Gilad Ben-Yossef <gilad@benyossef.com> +Date: Thu, 18 May 2017 16:29:24 +0300 +Subject: [PATCH 020/331] crypto: drbg - wait for crypto op not signal safe + +commit a5dfefb1c3f3db81662556393fd9283511e08430 upstream. + +drbg_kcapi_sym_ctr() was using wait_for_completion_interruptible() to +wait for completion of async crypto op but if a signal occurs it +may return before DMA ops of HW crypto provider finish, thus +corrupting the output buffer. + +Resolve this by using wait_for_completion() instead. + +Reported-by: Eric Biggers <ebiggers3@gmail.com> +Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + crypto/drbg.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +diff --git a/crypto/drbg.c b/crypto/drbg.c +index 053035b..123d211 100644 +--- a/crypto/drbg.c ++++ b/crypto/drbg.c +@@ -1768,9 +1768,8 @@ static int drbg_kcapi_sym_ctr(struct drbg_state *drbg, + break; + case -EINPROGRESS: + case -EBUSY: +- ret = wait_for_completion_interruptible( +- &drbg->ctr_completion); +- if (!ret && !drbg->ctr_async_err) { ++ wait_for_completion(&drbg->ctr_completion); ++ if (!drbg->ctr_async_err) { + reinit_completion(&drbg->ctr_completion); + break; + } +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0175-crypto-asymmetric_keys-handle-EBUSY-due-to-backlog-c.patch b/meta-snowyowl/recipes-kernel/linux/files/0175-crypto-asymmetric_keys-handle-EBUSY-due-to-backlog-c.patch new file mode 100755 index 00000000..52df2713 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0175-crypto-asymmetric_keys-handle-EBUSY-due-to-backlog-c.patch @@ -0,0 +1,40 @@ +From ae89eb389dd82c3ff6ec07f28019f7f474605827 Mon Sep 17 00:00:00 2001 +From: Gilad Ben-Yossef <gilad@benyossef.com> +Date: Thu, 18 May 2017 16:29:23 +0300 +Subject: [PATCH 021/331] crypto: asymmetric_keys - handle EBUSY due to backlog + correctly + +commit e68368aed56324e2e38d4f6b044bb8cf82077fc2 upstream. + +public_key_verify_signature() was passing the CRYPTO_TFM_REQ_MAY_BACKLOG +flag to akcipher_request_set_callback() but was not handling correctly +the case where a -EBUSY error could be returned from the call to +crypto_akcipher_verify() if backlog was used, possibly casuing +data corruption due to use-after-free of buffers. + +Resolve this by handling -EBUSY correctly. + +Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + crypto/asymmetric_keys/public_key.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/crypto/asymmetric_keys/public_key.c b/crypto/asymmetric_keys/public_key.c +index fd76b5f..4955eb6 100644 +--- a/crypto/asymmetric_keys/public_key.c ++++ b/crypto/asymmetric_keys/public_key.c +@@ -140,7 +140,7 @@ int public_key_verify_signature(const struct public_key *pkey, + * signature and returns that to us. + */ + ret = crypto_akcipher_verify(req); +- if (ret == -EINPROGRESS) { ++ if ((ret == -EINPROGRESS) || (ret == -EBUSY)) { + wait_for_completion(&compl.completion); + ret = compl.err; + } +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0176-crypto-Work-around-deallocated-stack-frame-reference.patch b/meta-snowyowl/recipes-kernel/linux/files/0176-crypto-Work-around-deallocated-stack-frame-reference.patch new file mode 100755 index 00000000..c1370fee --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0176-crypto-Work-around-deallocated-stack-frame-reference.patch @@ -0,0 +1,119 @@ +From ab03c8d27dd8c8f17ea773d34cc3e69af89c911f Mon Sep 17 00:00:00 2001 +From: David Miller <davem@davemloft.net> +Date: Fri, 2 Jun 2017 11:28:54 -0400 +Subject: [PATCH 028/331] crypto: Work around deallocated stack frame reference + gcc bug on sparc. + +commit d41519a69b35b10af7fda867fb9100df24fdf403 upstream. + +On sparc, if we have an alloca() like situation, as is the case with +SHASH_DESC_ON_STACK(), we can end up referencing deallocated stack +memory. The result can be that the value is clobbered if a trap +or interrupt arrives at just the right instruction. + +It only occurs if the function ends returning a value from that +alloca() area and that value can be placed into the return value +register using a single instruction. + +For example, in lib/libcrc32c.c:crc32c() we end up with a return +sequence like: + + return %i7+8 + lduw [%o5+16], %o0 ! MEM[(u32 *)__shash_desc.1_10 + 16B], + +%o5 holds the base of the on-stack area allocated for the shash +descriptor. But the return released the stack frame and the +register window. + +So if an intererupt arrives between 'return' and 'lduw', then +the value read at %o5+16 can be corrupted. + +Add a data compiler barrier to work around this problem. This is +exactly what the gcc fix will end up doing as well, and it absolutely +should not change the code generated for other cpus (unless gcc +on them has the same bug :-) + +With crucial insight from Eric Sandeen. + +Reported-by: Anatoly Pugachev <matorola@gmail.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + fs/btrfs/hash.c | 5 ++++- + fs/f2fs/f2fs.h | 5 ++++- + lib/libcrc32c.c | 6 ++++-- + 3 files changed, 12 insertions(+), 4 deletions(-) + +diff --git a/fs/btrfs/hash.c b/fs/btrfs/hash.c +index a97fdc1..baacc18 100644 +--- a/fs/btrfs/hash.c ++++ b/fs/btrfs/hash.c +@@ -38,6 +38,7 @@ u32 btrfs_crc32c(u32 crc, const void *address, unsigned int length) + { + SHASH_DESC_ON_STACK(shash, tfm); + u32 *ctx = (u32 *)shash_desc_ctx(shash); ++ u32 retval; + int err; + + shash->tfm = tfm; +@@ -47,5 +48,7 @@ u32 btrfs_crc32c(u32 crc, const void *address, unsigned int length) + err = crypto_shash_update(shash, address, length); + BUG_ON(err); + +- return *ctx; ++ retval = *ctx; ++ barrier_data(ctx); ++ return retval; + } +diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h +index 3a1640b..4051c24 100644 +--- a/fs/f2fs/f2fs.h ++++ b/fs/f2fs/f2fs.h +@@ -948,6 +948,7 @@ static inline u32 f2fs_crc32(struct f2fs_sb_info *sbi, const void *address, + { + SHASH_DESC_ON_STACK(shash, sbi->s_chksum_driver); + u32 *ctx = (u32 *)shash_desc_ctx(shash); ++ u32 retval; + int err; + + shash->tfm = sbi->s_chksum_driver; +@@ -957,7 +958,9 @@ static inline u32 f2fs_crc32(struct f2fs_sb_info *sbi, const void *address, + err = crypto_shash_update(shash, address, length); + BUG_ON(err); + +- return *ctx; ++ retval = *ctx; ++ barrier_data(ctx); ++ return retval; + } + + static inline bool f2fs_crc_valid(struct f2fs_sb_info *sbi, __u32 blk_crc, +diff --git a/lib/libcrc32c.c b/lib/libcrc32c.c +index 74a54b7..9f79547 100644 +--- a/lib/libcrc32c.c ++++ b/lib/libcrc32c.c +@@ -43,7 +43,7 @@ static struct crypto_shash *tfm; + u32 crc32c(u32 crc, const void *address, unsigned int length) + { + SHASH_DESC_ON_STACK(shash, tfm); +- u32 *ctx = (u32 *)shash_desc_ctx(shash); ++ u32 ret, *ctx = (u32 *)shash_desc_ctx(shash); + int err; + + shash->tfm = tfm; +@@ -53,7 +53,9 @@ u32 crc32c(u32 crc, const void *address, unsigned int length) + err = crypto_shash_update(shash, address, length); + BUG_ON(err); + +- return *ctx; ++ ret = *ctx; ++ barrier_data(ctx); ++ return ret; + } + + EXPORT_SYMBOL(crc32c); +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0177-crypto-drbg-Fixes-panic-in-wait_for_completion-call.patch b/meta-snowyowl/recipes-kernel/linux/files/0177-crypto-drbg-Fixes-panic-in-wait_for_completion-call.patch new file mode 100755 index 00000000..8b299a48 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0177-crypto-drbg-Fixes-panic-in-wait_for_completion-call.patch @@ -0,0 +1,35 @@ +From de190dfddee7280ff3405b9d5f4e04b8fd02d934 Mon Sep 17 00:00:00 2001 +From: Stephan Mueller <smueller@chronox.de> +Date: Fri, 26 May 2017 12:11:31 +0200 +Subject: [PATCH 048/331] crypto: drbg - Fixes panic in wait_for_completion + call + +commit b61929c654f2e725644935737c4c1ea9c741e2f8 upstream. + +Initialise ctr_completion variable before use. + +Cc: <stable@vger.kernel.org> +Signed-off-by: Harsh Jain <harshjain.prof@gmail.com> +Signed-off-by: Stephan Mueller <smueller@chronox.de> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + crypto/drbg.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/crypto/drbg.c b/crypto/drbg.c +index 123d211..8cac3d3 100644 +--- a/crypto/drbg.c ++++ b/crypto/drbg.c +@@ -1691,6 +1691,7 @@ static int drbg_init_sym_kernel(struct drbg_state *drbg) + return PTR_ERR(sk_tfm); + } + drbg->ctr_handle = sk_tfm; ++ init_completion(&drbg->ctr_completion); + + req = skcipher_request_alloc(sk_tfm, GFP_KERNEL); + if (!req) { +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0178-crypto-ccp-remove-unused-variable-qim.patch b/meta-snowyowl/recipes-kernel/linux/files/0178-crypto-ccp-remove-unused-variable-qim.patch new file mode 100755 index 00000000..eb02fe33 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0178-crypto-ccp-remove-unused-variable-qim.patch @@ -0,0 +1,41 @@ +From 42d4ce02a3b03ad632e5333c2671c2a571a72ac7 Mon Sep 17 00:00:00 2001 +From: Colin Ian King <colin.king@canonical.com> +Date: Thu, 12 Oct 2017 17:55:41 +0100 +Subject: [PATCH 323/331] crypto: ccp - remove unused variable qim + +Variable qim is assigned but never read, it is redundant and can +be removed. + +Cleans up clang warning: Value stored to 'qim' is never read + +Fixes: 4b394a232df7 ("crypto: ccp - Let a v5 CCP provide the same function as v3") +Signed-off-by: Colin Ian King <colin.king@canonical.com> +Acked-by: Gary R Hook <gary.hook@amd.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/ccp-dev-v5.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/crypto/ccp/ccp-dev-v5.c b/drivers/crypto/ccp/ccp-dev-v5.c +index 65604fc..44a4d27 100644 +--- a/drivers/crypto/ccp/ccp-dev-v5.c ++++ b/drivers/crypto/ccp/ccp-dev-v5.c +@@ -788,13 +788,12 @@ static int ccp5_init(struct ccp_device *ccp) + struct ccp_cmd_queue *cmd_q; + struct dma_pool *dma_pool; + char dma_pool_name[MAX_DMAPOOL_NAME_LEN]; +- unsigned int qmr, qim, i; ++ unsigned int qmr, i; + u64 status; + u32 status_lo, status_hi; + int ret; + + /* Find available queues */ +- qim = 0; + qmr = ioread32(ccp->io_regs + Q_MASK_REG); + for (i = 0; i < MAX_HW_QUEUES; i++) { + +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0179-crypto-ccp-use-ENOSPC-for-transient-busy-indication.patch b/meta-snowyowl/recipes-kernel/linux/files/0179-crypto-ccp-use-ENOSPC-for-transient-busy-indication.patch new file mode 100755 index 00000000..3d3358cd --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0179-crypto-ccp-use-ENOSPC-for-transient-busy-indication.patch @@ -0,0 +1,67 @@ +From 6328660d4d0a5d1233544a052be7ed21a0a4ad8b Mon Sep 17 00:00:00 2001 +From: Gilad Ben-Yossef <gilad@benyossef.com> +Date: Wed, 18 Oct 2017 08:00:34 +0100 +Subject: [PATCH 324/331] crypto: ccp - use -ENOSPC for transient busy + indication + +Replace -EBUSY with -ENOSPC when reporting transient busy +indication in the absence of backlog. + +Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> +Reviewed-by: Gary R Hook <gary.hook@amd.com> +Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/ccp-crypto-main.c | 8 +++----- + drivers/crypto/ccp/ccp-dev.c | 7 +++++-- + 2 files changed, 8 insertions(+), 7 deletions(-) + +diff --git a/drivers/crypto/ccp/ccp-crypto-main.c b/drivers/crypto/ccp/ccp-crypto-main.c +index 35a9de7..b95d199 100644 +--- a/drivers/crypto/ccp/ccp-crypto-main.c ++++ b/drivers/crypto/ccp/ccp-crypto-main.c +@@ -222,9 +222,10 @@ static int ccp_crypto_enqueue_cmd(struct ccp_crypto_cmd *crypto_cmd) + + /* Check if the cmd can/should be queued */ + if (req_queue.cmd_count >= CCP_CRYPTO_MAX_QLEN) { +- ret = -EBUSY; +- if (!(crypto_cmd->cmd->flags & CCP_CMD_MAY_BACKLOG)) ++ if (!(crypto_cmd->cmd->flags & CCP_CMD_MAY_BACKLOG)) { ++ ret = -ENOSPC; + goto e_lock; ++ } + } + + /* Look for an entry with the same tfm. If there is a cmd +@@ -243,9 +244,6 @@ static int ccp_crypto_enqueue_cmd(struct ccp_crypto_cmd *crypto_cmd) + ret = ccp_enqueue_cmd(crypto_cmd->cmd); + if (!ccp_crypto_success(ret)) + goto e_lock; /* Error, don't queue it */ +- if ((ret == -EBUSY) && +- !(crypto_cmd->cmd->flags & CCP_CMD_MAY_BACKLOG)) +- goto e_lock; /* Not backlogging, don't queue it */ + } + + if (req_queue.cmd_count >= CCP_CRYPTO_MAX_QLEN) { +diff --git a/drivers/crypto/ccp/ccp-dev.c b/drivers/crypto/ccp/ccp-dev.c +index 4e029b1..1b5035d 100644 +--- a/drivers/crypto/ccp/ccp-dev.c ++++ b/drivers/crypto/ccp/ccp-dev.c +@@ -292,9 +292,12 @@ int ccp_enqueue_cmd(struct ccp_cmd *cmd) + i = ccp->cmd_q_count; + + if (ccp->cmd_count >= MAX_CMD_QLEN) { +- ret = -EBUSY; +- if (cmd->flags & CCP_CMD_MAY_BACKLOG) ++ if (cmd->flags & CCP_CMD_MAY_BACKLOG) { ++ ret = -EBUSY; + list_add_tail(&cmd->entry, &ccp->backlog); ++ } else { ++ ret = -ENOSPC; ++ } + } else { + ret = -EINPROGRESS; + ccp->cmd_count++; +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0180-crypto-ccp-Build-the-AMD-secure-processor-driver-onl.patch b/meta-snowyowl/recipes-kernel/linux/files/0180-crypto-ccp-Build-the-AMD-secure-processor-driver-onl.patch new file mode 100755 index 00000000..53282c22 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0180-crypto-ccp-Build-the-AMD-secure-processor-driver-onl.patch @@ -0,0 +1,37 @@ +From 67e00a07d618698c2cca6704dabaa6276c6831b0 Mon Sep 17 00:00:00 2001 +From: Borislav Petkov <bp@suse.de> +Date: Mon, 4 Dec 2017 10:57:26 -0600 +Subject: [PATCH 325/331] crypto: ccp: Build the AMD secure processor driver + only with AMD CPU support + +This is AMD-specific hardware so present it in Kconfig only when AMD +CPU support is enabled or on ARM64 where it is also used. + +Signed-off-by: Borislav Petkov <bp@suse.de> +Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> +Reviewed-by: Gary R Hook <gary.hook@amd.com> +Cc: Brijesh Singh <brijesh.singh@amd.com> +Cc: Tom Lendacky <thomas.lendacky@amd.com> +Cc: Gary Hook <gary.hook@amd.com> +Cc: Herbert Xu <herbert@gondor.apana.org.au> +Cc: "David S. Miller" <davem@davemloft.net> +Cc: linux-crypto@vger.kernel.org +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/crypto/ccp/Kconfig b/drivers/crypto/ccp/Kconfig +index 6d62660..9c84f98 100644 +--- a/drivers/crypto/ccp/Kconfig ++++ b/drivers/crypto/ccp/Kconfig +@@ -1,5 +1,6 @@ + config CRYPTO_DEV_CCP_DD + tristate "Secure Processor device driver" ++ depends on CPU_SUP_AMD || ARM64 + default m + help + Provides AMD Secure Processor device driver. +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0181-crypto-ccp-Add-Platform-Security-Processor-PSP-devic.patch b/meta-snowyowl/recipes-kernel/linux/files/0181-crypto-ccp-Add-Platform-Security-Processor-PSP-devic.patch new file mode 100755 index 00000000..f40f4711 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0181-crypto-ccp-Add-Platform-Security-Processor-PSP-devic.patch @@ -0,0 +1,462 @@ +From 899458d8cedd0af7cf3e5fdbd1dbe50547b68db3 Mon Sep 17 00:00:00 2001 +From: Brijesh Singh <brijesh.singh@amd.com> +Date: Mon, 4 Dec 2017 10:57:28 -0600 +Subject: [PATCH 326/331] crypto: ccp: Add Platform Security Processor (PSP) + device support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The Platform Security Processor (PSP) is part of the AMD Secure +Processor (AMD-SP) functionality. The PSP is a dedicated processor +that provides support for key management commands in Secure Encrypted +Virtualization (SEV) mode, along with software-based Trusted Execution +Environment (TEE) to enable third-party trusted applications. + +Note that the key management functionality provided by the SEV firmware +can be used outside of the kvm-amd driver hence it doesn't need to +depend on CONFIG_KVM_AMD. + +Cc: Paolo Bonzini <pbonzini@redhat.com> +Cc: "Radim Krčmář" <rkrcmar@redhat.com> +Cc: Borislav Petkov <bp@suse.de> +Cc: Herbert Xu <herbert@gondor.apana.org.au> +Cc: Gary Hook <gary.hook@amd.com> +Cc: Tom Lendacky <thomas.lendacky@amd.com> +Cc: linux-crypto@vger.kernel.org +Cc: kvm@vger.kernel.org +Cc: linux-kernel@vger.kernel.org +Improvements-by: Borislav Petkov <bp@suse.de> +Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> +Reviewed-by: Borislav Petkov <bp@suse.de> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/crypto/ccp/Kconfig | 11 +++++ + drivers/crypto/ccp/Makefile | 1 + + drivers/crypto/ccp/psp-dev.c | 105 +++++++++++++++++++++++++++++++++++++++++++ + drivers/crypto/ccp/psp-dev.h | 59 ++++++++++++++++++++++++ + drivers/crypto/ccp/sp-dev.c | 26 +++++++++++ + drivers/crypto/ccp/sp-dev.h | 24 +++++++++- + drivers/crypto/ccp/sp-pci.c | 52 +++++++++++++++++++++ + 7 files changed, 277 insertions(+), 1 deletion(-) + create mode 100644 drivers/crypto/ccp/psp-dev.c + create mode 100644 drivers/crypto/ccp/psp-dev.h + +diff --git a/drivers/crypto/ccp/Kconfig b/drivers/crypto/ccp/Kconfig +index 9c84f98..b9dfae4 100644 +--- a/drivers/crypto/ccp/Kconfig ++++ b/drivers/crypto/ccp/Kconfig +@@ -33,3 +33,14 @@ config CRYPTO_DEV_CCP_CRYPTO + Support for using the cryptographic API with the AMD Cryptographic + Coprocessor. This module supports offload of SHA and AES algorithms. + If you choose 'M' here, this module will be called ccp_crypto. ++ ++config CRYPTO_DEV_SP_PSP ++ bool "Platform Security Processor (PSP) device" ++ default y ++ depends on CRYPTO_DEV_CCP_DD && X86_64 ++ help ++ Provide support for the AMD Platform Security Processor (PSP). ++ The PSP is a dedicated processor that provides support for key ++ management commands in Secure Encrypted Virtualization (SEV) mode, ++ along with software-based Trusted Execution Environment (TEE) to ++ enable third-party trusted applications. +diff --git a/drivers/crypto/ccp/Makefile b/drivers/crypto/ccp/Makefile +index 57f8deb..008bae7 100644 +--- a/drivers/crypto/ccp/Makefile ++++ b/drivers/crypto/ccp/Makefile +@@ -7,6 +7,7 @@ ccp-$(CONFIG_CRYPTO_DEV_SP_CCP) += ccp-dev.o \ + ccp-dmaengine.o \ + ccp-debugfs.o + ccp-$(CONFIG_PCI) += sp-pci.o ++ccp-$(CONFIG_CRYPTO_DEV_SP_PSP) += psp-dev.o + + obj-$(CONFIG_CRYPTO_DEV_CCP_CRYPTO) += ccp-crypto.o + ccp-crypto-objs := ccp-crypto-main.o \ +diff --git a/drivers/crypto/ccp/psp-dev.c b/drivers/crypto/ccp/psp-dev.c +new file mode 100644 +index 0000000..b5789f8 +--- /dev/null ++++ b/drivers/crypto/ccp/psp-dev.c +@@ -0,0 +1,105 @@ ++/* ++ * AMD Platform Security Processor (PSP) interface ++ * ++ * Copyright (C) 2016-2017 Advanced Micro Devices, Inc. ++ * ++ * Author: Brijesh Singh <brijesh.singh@amd.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/kthread.h> ++#include <linux/sched.h> ++#include <linux/interrupt.h> ++#include <linux/spinlock.h> ++#include <linux/spinlock_types.h> ++#include <linux/types.h> ++#include <linux/mutex.h> ++#include <linux/delay.h> ++#include <linux/hw_random.h> ++#include <linux/ccp.h> ++ ++#include "sp-dev.h" ++#include "psp-dev.h" ++ ++static struct psp_device *psp_alloc_struct(struct sp_device *sp) ++{ ++ struct device *dev = sp->dev; ++ struct psp_device *psp; ++ ++ psp = devm_kzalloc(dev, sizeof(*psp), GFP_KERNEL); ++ if (!psp) ++ return NULL; ++ ++ psp->dev = dev; ++ psp->sp = sp; ++ ++ snprintf(psp->name, sizeof(psp->name), "psp-%u", sp->ord); ++ ++ return psp; ++} ++ ++static irqreturn_t psp_irq_handler(int irq, void *data) ++{ ++ return IRQ_HANDLED; ++} ++ ++int psp_dev_init(struct sp_device *sp) ++{ ++ struct device *dev = sp->dev; ++ struct psp_device *psp; ++ int ret; ++ ++ ret = -ENOMEM; ++ psp = psp_alloc_struct(sp); ++ if (!psp) ++ goto e_err; ++ ++ sp->psp_data = psp; ++ ++ psp->vdata = (struct psp_vdata *)sp->dev_vdata->psp_vdata; ++ if (!psp->vdata) { ++ ret = -ENODEV; ++ dev_err(dev, "missing driver data\n"); ++ goto e_err; ++ } ++ ++ psp->io_regs = sp->io_map + psp->vdata->offset; ++ ++ /* Disable and clear interrupts until ready */ ++ iowrite32(0, psp->io_regs + PSP_P2CMSG_INTEN); ++ iowrite32(-1, psp->io_regs + PSP_P2CMSG_INTSTS); ++ ++ /* Request an irq */ ++ ret = sp_request_psp_irq(psp->sp, psp_irq_handler, psp->name, psp); ++ if (ret) { ++ dev_err(dev, "psp: unable to allocate an IRQ\n"); ++ goto e_err; ++ } ++ ++ if (sp->set_psp_master_device) ++ sp->set_psp_master_device(sp); ++ ++ /* Enable interrupt */ ++ iowrite32(-1, psp->io_regs + PSP_P2CMSG_INTEN); ++ ++ return 0; ++ ++e_err: ++ sp->psp_data = NULL; ++ ++ dev_notice(dev, "psp initialization failed\n"); ++ ++ return ret; ++} ++ ++void psp_dev_destroy(struct sp_device *sp) ++{ ++ struct psp_device *psp = sp->psp_data; ++ ++ sp_free_psp_irq(sp, psp); ++} +diff --git a/drivers/crypto/ccp/psp-dev.h b/drivers/crypto/ccp/psp-dev.h +new file mode 100644 +index 0000000..55b7808 +--- /dev/null ++++ b/drivers/crypto/ccp/psp-dev.h +@@ -0,0 +1,59 @@ ++/* ++ * AMD Platform Security Processor (PSP) interface driver ++ * ++ * Copyright (C) 2017 Advanced Micro Devices, Inc. ++ * ++ * Author: Brijesh Singh <brijesh.singh@amd.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __PSP_DEV_H__ ++#define __PSP_DEV_H__ ++ ++#include <linux/device.h> ++#include <linux/pci.h> ++#include <linux/spinlock.h> ++#include <linux/mutex.h> ++#include <linux/list.h> ++#include <linux/wait.h> ++#include <linux/dmapool.h> ++#include <linux/hw_random.h> ++#include <linux/bitops.h> ++#include <linux/interrupt.h> ++#include <linux/irqreturn.h> ++#include <linux/dmaengine.h> ++ ++#include "sp-dev.h" ++ ++#define PSP_P2CMSG_INTEN 0x0110 ++#define PSP_P2CMSG_INTSTS 0x0114 ++ ++#define PSP_C2PMSG_ATTR_0 0x0118 ++#define PSP_C2PMSG_ATTR_1 0x011c ++#define PSP_C2PMSG_ATTR_2 0x0120 ++#define PSP_C2PMSG_ATTR_3 0x0124 ++#define PSP_P2CMSG_ATTR_0 0x0128 ++ ++#define PSP_CMDRESP_CMD_SHIFT 16 ++#define PSP_CMDRESP_IOC BIT(0) ++#define PSP_CMDRESP_RESP BIT(31) ++#define PSP_CMDRESP_ERR_MASK 0xffff ++ ++#define MAX_PSP_NAME_LEN 16 ++ ++struct psp_device { ++ struct list_head entry; ++ ++ struct psp_vdata *vdata; ++ char name[MAX_PSP_NAME_LEN]; ++ ++ struct device *dev; ++ struct sp_device *sp; ++ ++ void __iomem *io_regs; ++}; ++ ++#endif /* __PSP_DEV_H */ +diff --git a/drivers/crypto/ccp/sp-dev.c b/drivers/crypto/ccp/sp-dev.c +index bef387c8..cf101c0 100644 +--- a/drivers/crypto/ccp/sp-dev.c ++++ b/drivers/crypto/ccp/sp-dev.c +@@ -198,6 +198,8 @@ int sp_init(struct sp_device *sp) + if (sp->dev_vdata->ccp_vdata) + ccp_dev_init(sp); + ++ if (sp->dev_vdata->psp_vdata) ++ psp_dev_init(sp); + return 0; + } + +@@ -206,6 +208,9 @@ void sp_destroy(struct sp_device *sp) + if (sp->dev_vdata->ccp_vdata) + ccp_dev_destroy(sp); + ++ if (sp->dev_vdata->psp_vdata) ++ psp_dev_destroy(sp); ++ + sp_del_device(sp); + } + +@@ -237,6 +242,27 @@ int sp_resume(struct sp_device *sp) + } + #endif + ++struct sp_device *sp_get_psp_master_device(void) ++{ ++ struct sp_device *i, *ret = NULL; ++ unsigned long flags; ++ ++ write_lock_irqsave(&sp_unit_lock, flags); ++ if (list_empty(&sp_units)) ++ goto unlock; ++ ++ list_for_each_entry(i, &sp_units, entry) { ++ if (i->psp_data) ++ break; ++ } ++ ++ if (i->get_psp_master_device) ++ ret = i->get_psp_master_device(); ++unlock: ++ write_unlock_irqrestore(&sp_unit_lock, flags); ++ return ret; ++} ++ + static int __init sp_mod_init(void) + { + #ifdef CONFIG_X86 +diff --git a/drivers/crypto/ccp/sp-dev.h b/drivers/crypto/ccp/sp-dev.h +index 5ab486a..909cf3e 100644 +--- a/drivers/crypto/ccp/sp-dev.h ++++ b/drivers/crypto/ccp/sp-dev.h +@@ -42,12 +42,17 @@ struct ccp_vdata { + const unsigned int offset; + const unsigned int rsamax; + }; ++ ++struct psp_vdata { ++ const unsigned int offset; ++}; ++ + /* Structure to hold SP device data */ + struct sp_dev_vdata { + const unsigned int bar; + + const struct ccp_vdata *ccp_vdata; +- void *psp_vdata; ++ const struct psp_vdata *psp_vdata; + }; + + struct sp_device { +@@ -68,6 +73,10 @@ struct sp_device { + /* DMA caching attribute support */ + unsigned int axcache; + ++ /* get and set master device */ ++ struct sp_device*(*get_psp_master_device)(void); ++ void (*set_psp_master_device)(struct sp_device *); ++ + bool irq_registered; + bool use_tasklet; + +@@ -103,6 +112,7 @@ void sp_free_ccp_irq(struct sp_device *sp, void *data); + int sp_request_psp_irq(struct sp_device *sp, irq_handler_t handler, + const char *name, void *data); + void sp_free_psp_irq(struct sp_device *sp, void *data); ++struct sp_device *sp_get_psp_master_device(void); + + #ifdef CONFIG_CRYPTO_DEV_SP_CCP + +@@ -130,4 +140,16 @@ static inline int ccp_dev_resume(struct sp_device *sp) + } + #endif /* CONFIG_CRYPTO_DEV_SP_CCP */ + ++#ifdef CONFIG_CRYPTO_DEV_SP_PSP ++ ++int psp_dev_init(struct sp_device *sp); ++void psp_dev_destroy(struct sp_device *sp); ++ ++#else /* !CONFIG_CRYPTO_DEV_SP_PSP */ ++ ++static inline int psp_dev_init(struct sp_device *sp) { return 0; } ++static inline void psp_dev_destroy(struct sp_device *sp) { } ++ ++#endif /* CONFIG_CRYPTO_DEV_SP_PSP */ ++ + #endif +diff --git a/drivers/crypto/ccp/sp-pci.c b/drivers/crypto/ccp/sp-pci.c +index 9859aa6..f5f43c5 100644 +--- a/drivers/crypto/ccp/sp-pci.c ++++ b/drivers/crypto/ccp/sp-pci.c +@@ -25,6 +25,7 @@ + #include <linux/ccp.h> + + #include "ccp-dev.h" ++#include "psp-dev.h" + + #define MSIX_VECTORS 2 + +@@ -32,6 +33,7 @@ struct sp_pci { + int msix_count; + struct msix_entry msix_entry[MSIX_VECTORS]; + }; ++static struct sp_device *sp_dev_master; + + static int sp_get_msix_irqs(struct sp_device *sp) + { +@@ -108,6 +110,45 @@ static void sp_free_irqs(struct sp_device *sp) + sp->psp_irq = 0; + } + ++static bool sp_pci_is_master(struct sp_device *sp) ++{ ++ struct device *dev_cur, *dev_new; ++ struct pci_dev *pdev_cur, *pdev_new; ++ ++ dev_new = sp->dev; ++ dev_cur = sp_dev_master->dev; ++ ++ pdev_new = to_pci_dev(dev_new); ++ pdev_cur = to_pci_dev(dev_cur); ++ ++ if (pdev_new->bus->number < pdev_cur->bus->number) ++ return true; ++ ++ if (PCI_SLOT(pdev_new->devfn) < PCI_SLOT(pdev_cur->devfn)) ++ return true; ++ ++ if (PCI_FUNC(pdev_new->devfn) < PCI_FUNC(pdev_cur->devfn)) ++ return true; ++ ++ return false; ++} ++ ++static void psp_set_master(struct sp_device *sp) ++{ ++ if (!sp_dev_master) { ++ sp_dev_master = sp; ++ return; ++ } ++ ++ if (sp_pci_is_master(sp)) ++ sp_dev_master = sp; ++} ++ ++static struct sp_device *psp_get_master(void) ++{ ++ return sp_dev_master; ++} ++ + static int sp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) + { + struct sp_device *sp; +@@ -166,6 +207,8 @@ static int sp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) + goto e_err; + + pci_set_master(pdev); ++ sp->set_psp_master_device = psp_set_master; ++ sp->get_psp_master_device = psp_get_master; + + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); + if (ret) { +@@ -225,6 +268,12 @@ static int sp_pci_resume(struct pci_dev *pdev) + } + #endif + ++#ifdef CONFIG_CRYPTO_DEV_SP_PSP ++static const struct psp_vdata psp_entry = { ++ .offset = 0x10500, ++}; ++#endif ++ + static const struct sp_dev_vdata dev_vdata[] = { + { + .bar = 2, +@@ -237,6 +286,9 @@ static const struct sp_dev_vdata dev_vdata[] = { + #ifdef CONFIG_CRYPTO_DEV_SP_CCP + .ccp_vdata = &ccpv5a, + #endif ++#ifdef CONFIG_CRYPTO_DEV_SP_PSP ++ .psp_vdata = &psp_entry ++#endif + }, + { + .bar = 2, +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0182-crypto-ccp-Define-SEV-userspace-ioctl-and-command-id.patch b/meta-snowyowl/recipes-kernel/linux/files/0182-crypto-ccp-Define-SEV-userspace-ioctl-and-command-id.patch new file mode 100755 index 00000000..ce7c959a --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0182-crypto-ccp-Define-SEV-userspace-ioctl-and-command-id.patch @@ -0,0 +1,182 @@ +From ad8faa2762dbb0a5cfe803bb9e442f911944b975 Mon Sep 17 00:00:00 2001 +From: Brijesh Singh <brijesh.singh@amd.com> +Date: Mon, 4 Dec 2017 10:57:27 -0600 +Subject: [PATCH 327/331] crypto: ccp: Define SEV userspace ioctl and command + id +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add a include file which defines the ioctl and command id used for +issuing SEV platform management specific commands. + +Cc: Paolo Bonzini <pbonzini@redhat.com> +Cc: "Radim Krčmář" <rkrcmar@redhat.com> +Cc: Borislav Petkov <bp@suse.de> +Cc: Herbert Xu <herbert@gondor.apana.org.au> +Cc: Gary Hook <gary.hook@amd.com> +Cc: Tom Lendacky <thomas.lendacky@amd.com> +Cc: linux-crypto@vger.kernel.org +Cc: kvm@vger.kernel.org +Cc: linux-kernel@vger.kernel.org +Improvements-by: Borislav Petkov <bp@suse.de> +Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> +Reviewed-by: Borislav Petkov <bp@suse.de> +Acked-by: Gary R Hook <gary.hook@amd.com> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + include/uapi/linux/psp-sev.h | 142 +++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 142 insertions(+) + create mode 100644 include/uapi/linux/psp-sev.h + +diff --git a/include/uapi/linux/psp-sev.h b/include/uapi/linux/psp-sev.h +new file mode 100644 +index 0000000..3d77fe9 +--- /dev/null ++++ b/include/uapi/linux/psp-sev.h +@@ -0,0 +1,142 @@ ++/* ++ * Userspace interface for AMD Secure Encrypted Virtualization (SEV) ++ * platform management commands. ++ * ++ * Copyright (C) 2016-2017 Advanced Micro Devices, Inc. ++ * ++ * Author: Brijesh Singh <brijesh.singh@amd.com> ++ * ++ * SEV spec 0.14 is available at: ++ * http://support.amd.com/TechDocs/55766_SEV-KM%20API_Specification.pdf ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __PSP_SEV_USER_H__ ++#define __PSP_SEV_USER_H__ ++ ++#include <linux/types.h> ++ ++/** ++ * SEV platform commands ++ */ ++enum { ++ SEV_FACTORY_RESET = 0, ++ SEV_PLATFORM_STATUS, ++ SEV_PEK_GEN, ++ SEV_PEK_CSR, ++ SEV_PDH_GEN, ++ SEV_PDH_CERT_EXPORT, ++ SEV_PEK_CERT_IMPORT, ++ ++ SEV_MAX, ++}; ++ ++/** ++ * SEV Firmware status code ++ */ ++typedef enum { ++ SEV_RET_SUCCESS = 0, ++ SEV_RET_INVALID_PLATFORM_STATE, ++ SEV_RET_INVALID_GUEST_STATE, ++ SEV_RET_INAVLID_CONFIG, ++ SEV_RET_INVALID_len, ++ SEV_RET_ALREADY_OWNED, ++ SEV_RET_INVALID_CERTIFICATE, ++ SEV_RET_POLICY_FAILURE, ++ SEV_RET_INACTIVE, ++ SEV_RET_INVALID_ADDRESS, ++ SEV_RET_BAD_SIGNATURE, ++ SEV_RET_BAD_MEASUREMENT, ++ SEV_RET_ASID_OWNED, ++ SEV_RET_INVALID_ASID, ++ SEV_RET_WBINVD_REQUIRED, ++ SEV_RET_DFFLUSH_REQUIRED, ++ SEV_RET_INVALID_GUEST, ++ SEV_RET_INVALID_COMMAND, ++ SEV_RET_ACTIVE, ++ SEV_RET_HWSEV_RET_PLATFORM, ++ SEV_RET_HWSEV_RET_UNSAFE, ++ SEV_RET_UNSUPPORTED, ++ SEV_RET_MAX, ++} sev_ret_code; ++ ++/** ++ * struct sev_user_data_status - PLATFORM_STATUS command parameters ++ * ++ * @major: major API version ++ * @minor: minor API version ++ * @state: platform state ++ * @flags: platform config flags ++ * @build: firmware build id for API version ++ * @guest_count: number of active guests ++ */ ++struct sev_user_data_status { ++ __u8 api_major; /* Out */ ++ __u8 api_minor; /* Out */ ++ __u8 state; /* Out */ ++ __u32 flags; /* Out */ ++ __u8 build; /* Out */ ++ __u32 guest_count; /* Out */ ++} __packed; ++ ++/** ++ * struct sev_user_data_pek_csr - PEK_CSR command parameters ++ * ++ * @address: PEK certificate chain ++ * @length: length of certificate ++ */ ++struct sev_user_data_pek_csr { ++ __u64 address; /* In */ ++ __u32 length; /* In/Out */ ++} __packed; ++ ++/** ++ * struct sev_user_data_cert_import - PEK_CERT_IMPORT command parameters ++ * ++ * @pek_address: PEK certificate chain ++ * @pek_len: length of PEK certificate ++ * @oca_address: OCA certificate chain ++ * @oca_len: length of OCA certificate ++ */ ++struct sev_user_data_pek_cert_import { ++ __u64 pek_cert_address; /* In */ ++ __u32 pek_cert_len; /* In */ ++ __u64 oca_cert_address; /* In */ ++ __u32 oca_cert_len; /* In */ ++} __packed; ++ ++/** ++ * struct sev_user_data_pdh_cert_export - PDH_CERT_EXPORT command parameters ++ * ++ * @pdh_address: PDH certificate address ++ * @pdh_len: length of PDH certificate ++ * @cert_chain_address: PDH certificate chain ++ * @cert_chain_len: length of PDH certificate chain ++ */ ++struct sev_user_data_pdh_cert_export { ++ __u64 pdh_cert_address; /* In */ ++ __u32 pdh_cert_len; /* In/Out */ ++ __u64 cert_chain_address; /* In */ ++ __u32 cert_chain_len; /* In/Out */ ++} __packed; ++ ++/** ++ * struct sev_issue_cmd - SEV ioctl parameters ++ * ++ * @cmd: SEV commands to execute ++ * @opaque: pointer to the command structure ++ * @error: SEV FW return code on failure ++ */ ++struct sev_issue_cmd { ++ __u32 cmd; /* In */ ++ __u64 data; /* In */ ++ __u32 error; /* Out */ ++} __packed; ++ ++#define SEV_IOC_TYPE 'S' ++#define SEV_ISSUE_CMD _IOWR(SEV_IOC_TYPE, 0x0, struct sev_issue_cmd) ++ ++#endif /* __PSP_USER_SEV_H */ +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0183-mqueue-fix-a-use-after-free-in-sys_mq_notify.patch b/meta-snowyowl/recipes-kernel/linux/files/0183-mqueue-fix-a-use-after-free-in-sys_mq_notify.patch new file mode 100755 index 00000000..8e6f87ea --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0183-mqueue-fix-a-use-after-free-in-sys_mq_notify.patch @@ -0,0 +1,52 @@ +From 9e08c00a65d1228febf7e9b221b5c923e14705f6 Mon Sep 17 00:00:00 2001 +From: Cong Wang <xiyou.wangcong@gmail.com> +Date: Sun, 9 Jul 2017 13:19:55 -0700 +Subject: [PATCH 049/331] mqueue: fix a use-after-free in sys_mq_notify() + +commit f991af3daabaecff34684fd51fac80319d1baad1 upstream. + +The retry logic for netlink_attachskb() inside sys_mq_notify() +is nasty and vulnerable: + +1) The sock refcnt is already released when retry is needed +2) The fd is controllable by user-space because we already + release the file refcnt + +so we when retry but the fd has been just closed by user-space +during this small window, we end up calling netlink_detachskb() +on the error path which releases the sock again, later when +the user-space closes this socket a use-after-free could be +triggered. + +Setting 'sock' to NULL here should be sufficient to fix it. + +Reported-by: GeneBlue <geneblue.mail@gmail.com> +Signed-off-by: Cong Wang <xiyou.wangcong@gmail.com> +Cc: Andrew Morton <akpm@linux-foundation.org> +Cc: Manfred Spraul <manfred@colorfullife.com> +Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + ipc/mqueue.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/ipc/mqueue.c b/ipc/mqueue.c +index 8cbd6e6..28a142f 100644 +--- a/ipc/mqueue.c ++++ b/ipc/mqueue.c +@@ -1249,8 +1249,10 @@ SYSCALL_DEFINE2(mq_notify, mqd_t, mqdes, + + timeo = MAX_SCHEDULE_TIMEOUT; + ret = netlink_attachskb(sock, nc, &timeo, NULL); +- if (ret == 1) ++ if (ret == 1) { ++ sock = NULL; + goto retry; ++ } + if (ret) { + sock = NULL; + nc = NULL; +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0184-i2c-designware-Fix-system-suspend.patch b/meta-snowyowl/recipes-kernel/linux/files/0184-i2c-designware-Fix-system-suspend.patch new file mode 100755 index 00000000..d03304cb --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0184-i2c-designware-Fix-system-suspend.patch @@ -0,0 +1,95 @@ +From c446f04b979d45674b2d0d0b560a40c81119fa05 Mon Sep 17 00:00:00 2001 +From: Ulf Hansson <ulf.hansson@linaro.org> +Date: Wed, 9 Aug 2017 15:28:22 +0200 +Subject: [PATCH 069/331] i2c: designware: Fix system suspend + +commit a23318feeff662c8d25d21623daebdd2e55ec221 upstream. + +The commit 8503ff166504 ("i2c: designware: Avoid unnecessary resuming +during system suspend"), may suggest to the PM core to try out the so +called direct_complete path for system sleep. In this path, the PM core +treats a runtime suspended device as it's already in a proper low power +state for system sleep, which makes it skip calling the system sleep +callbacks for the device, except for the ->prepare() and the ->complete() +callbacks. + +However, the PM core may unset the direct_complete flag for a parent +device, in case its child device are being system suspended before. In this +scenario, the PM core invokes the system sleep callbacks, no matter if the +device is runtime suspended or not. + +Particularly in cases of an existing i2c slave device, the above path is +triggered, which breaks the assumption that the i2c device is always +runtime resumed whenever the dw_i2c_plat_suspend() is being called. + +More precisely, dw_i2c_plat_suspend() calls clk_core_disable() and +clk_core_unprepare(), for an already disabled/unprepared clock, leading to +a splat in the log about clocks calls being wrongly balanced and breaking +system sleep. + +To still allow the direct_complete path in cases when it's possible, but +also to keep the fix simple, let's runtime resume the i2c device in the +->suspend() callback, before continuing to put the device into low power +state. + +Note, in cases when the i2c device is attached to the ACPI PM domain, this +problem doesn't occur, because ACPI's ->suspend() callback, assigned to +acpi_subsys_suspend(), already calls pm_runtime_resume() for the device. + +It should also be noted that this change does not fix commit 8503ff166504 +("i2c: designware: Avoid unnecessary resuming during system suspend"). +Because for the non-ACPI case, the system sleep support was already broken +prior that point. + +Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> +Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> +Tested-by: John Stultz <john.stultz@linaro.org> +Tested-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> +Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> +Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> +Signed-off-by: Wolfram Sang <wsa@the-dreams.de> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/i2c/busses/i2c-designware-platdrv.c | 14 ++++++++++++-- + 1 file changed, 12 insertions(+), 2 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c +index 0b42a12..b42d95f 100644 +--- a/drivers/i2c/busses/i2c-designware-platdrv.c ++++ b/drivers/i2c/busses/i2c-designware-platdrv.c +@@ -319,7 +319,7 @@ static void dw_i2c_plat_complete(struct device *dev) + #endif + + #ifdef CONFIG_PM +-static int dw_i2c_plat_suspend(struct device *dev) ++static int dw_i2c_plat_runtime_suspend(struct device *dev) + { + struct platform_device *pdev = to_platform_device(dev); + struct dw_i2c_dev *i_dev = platform_get_drvdata(pdev); +@@ -343,11 +343,21 @@ static int dw_i2c_plat_resume(struct device *dev) + return 0; + } + ++#ifdef CONFIG_PM_SLEEP ++static int dw_i2c_plat_suspend(struct device *dev) ++{ ++ pm_runtime_resume(dev); ++ return dw_i2c_plat_runtime_suspend(dev); ++} ++#endif ++ + static const struct dev_pm_ops dw_i2c_dev_pm_ops = { + .prepare = dw_i2c_plat_prepare, + .complete = dw_i2c_plat_complete, + SET_SYSTEM_SLEEP_PM_OPS(dw_i2c_plat_suspend, dw_i2c_plat_resume) +- SET_RUNTIME_PM_OPS(dw_i2c_plat_suspend, dw_i2c_plat_resume, NULL) ++ SET_RUNTIME_PM_OPS(dw_i2c_plat_runtime_suspend, ++ dw_i2c_plat_resume, ++ NULL) + }; + + #define DW_I2C_DEV_PMOPS (&dw_i2c_dev_pm_ops) +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0185-iommu-dma-Don-t-reserve-PCI-I-O-windows.patch b/meta-snowyowl/recipes-kernel/linux/files/0185-iommu-dma-Don-t-reserve-PCI-I-O-windows.patch new file mode 100755 index 00000000..eeb002de --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0185-iommu-dma-Don-t-reserve-PCI-I-O-windows.patch @@ -0,0 +1,39 @@ +From 2f2373b38365aa0e21b45cfed35b830dccca4257 Mon Sep 17 00:00:00 2001 +From: Robin Murphy <robin.murphy@arm.com> +Date: Thu, 16 Mar 2017 17:00:17 +0000 +Subject: [PATCH 038/331] iommu/dma: Don't reserve PCI I/O windows + +commit 938f1bbe35e3a7cb07e1fa7c512e2ef8bb866bdf upstream. + +Even if a host controller's CPU-side MMIO windows into PCI I/O space do +happen to leak into PCI memory space such that it might treat them as +peer addresses, trying to reserve the corresponding I/O space addresses +doesn't do anything to help solve that problem. Stop doing a silly thing. + +Fixes: fade1ec055dc ("iommu/dma: Avoid PCI host bridge windows") +Reviewed-by: Eric Auger <eric.auger@redhat.com> +Signed-off-by: Robin Murphy <robin.murphy@arm.com> +Signed-off-by: Joerg Roedel <jroedel@suse.de> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/iommu/dma-iommu.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c +index c5ab866..1520e7f 100644 +--- a/drivers/iommu/dma-iommu.c ++++ b/drivers/iommu/dma-iommu.c +@@ -112,8 +112,7 @@ static void iova_reserve_pci_windows(struct pci_dev *dev, + unsigned long lo, hi; + + resource_list_for_each_entry(window, &bridge->windows) { +- if (resource_type(window->res) != IORESOURCE_MEM && +- resource_type(window->res) != IORESOURCE_IO) ++ if (resource_type(window->res) != IORESOURCE_MEM) + continue; + + lo = iova_pfn(iovad, window->res->start - window->offset); +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0186-iommu-amd-Fix-incorrect-error-handling-in-amd_iommu_.patch b/meta-snowyowl/recipes-kernel/linux/files/0186-iommu-amd-Fix-incorrect-error-handling-in-amd_iommu_.patch new file mode 100755 index 00000000..ae49a732 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0186-iommu-amd-Fix-incorrect-error-handling-in-amd_iommu_.patch @@ -0,0 +1,41 @@ +From fecc4e051f43d6bc2d46d6226b7a036147226d5e Mon Sep 17 00:00:00 2001 +From: Pan Bian <bianpan2016@163.com> +Date: Sun, 23 Apr 2017 18:23:21 +0800 +Subject: [PATCH 039/331] iommu/amd: Fix incorrect error handling in + amd_iommu_bind_pasid() + +commit 73dbd4a4230216b6a5540a362edceae0c9b4876b upstream. + +In function amd_iommu_bind_pasid(), the control flow jumps +to label out_free when pasid_state->mm and mm is NULL. And +mmput(mm) is called. In function mmput(mm), mm is +referenced without validation. This will result in a NULL +dereference bug. This patch fixes the bug. + +Signed-off-by: Pan Bian <bianpan2016@163.com> +Fixes: f0aac63b873b ('iommu/amd: Don't hold a reference to mm_struct') +Signed-off-by: Joerg Roedel <jroedel@suse.de> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/iommu/amd_iommu_v2.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/iommu/amd_iommu_v2.c b/drivers/iommu/amd_iommu_v2.c +index f8ed8c9..a0b4ac6 100644 +--- a/drivers/iommu/amd_iommu_v2.c ++++ b/drivers/iommu/amd_iommu_v2.c +@@ -695,9 +695,9 @@ int amd_iommu_bind_pasid(struct pci_dev *pdev, int pasid, + + out_unregister: + mmu_notifier_unregister(&pasid_state->mn, mm); ++ mmput(mm); + + out_free: +- mmput(mm); + free_pasid_state(pasid_state); + + out: +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0187-iommu-amd-Fix-interrupt-remapping-when-disable-guest.patch b/meta-snowyowl/recipes-kernel/linux/files/0187-iommu-amd-Fix-interrupt-remapping-when-disable-guest.patch new file mode 100755 index 00000000..0afa767f --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0187-iommu-amd-Fix-interrupt-remapping-when-disable-guest.patch @@ -0,0 +1,59 @@ +From 59a13724c78977c316184ee4efbf00e82f70fe50 Mon Sep 17 00:00:00 2001 +From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> +Date: Mon, 26 Jun 2017 04:28:04 -0500 +Subject: [PATCH 040/331] iommu/amd: Fix interrupt remapping when disable + guest_mode + +commit 84a21dbdef0b96d773599c33c2afbb002198d303 upstream. + +Pass-through devices to VM guest can get updated IRQ affinity +information via irq_set_affinity() when not running in guest mode. +Currently, AMD IOMMU driver in GA mode ignores the updated information +if the pass-through device is setup to use vAPIC regardless of guest_mode. +This could cause invalid interrupt remapping. + +Also, the guest_mode bit should be set and cleared only when +SVM updates posted-interrupt interrupt remapping information. + +Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> +Cc: Joerg Roedel <jroedel@suse.de> +Fixes: d98de49a53e48 ('iommu/amd: Enable vAPIC interrupt remapping mode by default') +Signed-off-by: Joerg Roedel <jroedel@suse.de> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/iommu/amd_iommu.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c +index 11a13b5..41800b6 100644 +--- a/drivers/iommu/amd_iommu.c ++++ b/drivers/iommu/amd_iommu.c +@@ -3857,11 +3857,9 @@ static void irte_ga_prepare(void *entry, + u8 vector, u32 dest_apicid, int devid) + { + struct irte_ga *irte = (struct irte_ga *) entry; +- struct iommu_dev_data *dev_data = search_dev_data(devid); + + irte->lo.val = 0; + irte->hi.val = 0; +- irte->lo.fields_remap.guest_mode = dev_data ? dev_data->use_vapic : 0; + irte->lo.fields_remap.int_type = delivery_mode; + irte->lo.fields_remap.dm = dest_mode; + irte->hi.fields.vector = vector; +@@ -3917,10 +3915,10 @@ static void irte_ga_set_affinity(void *entry, u16 devid, u16 index, + struct irte_ga *irte = (struct irte_ga *) entry; + struct iommu_dev_data *dev_data = search_dev_data(devid); + +- if (!dev_data || !dev_data->use_vapic) { ++ if (!dev_data || !dev_data->use_vapic || ++ !irte->lo.fields_remap.guest_mode) { + irte->hi.fields.vector = vector; + irte->lo.fields_remap.destination = dest_apicid; +- irte->lo.fields_remap.guest_mode = 0; + modify_irte_ga(devid, index, irte, NULL); + } + } +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0188-iommu-amd-Enable-ga_log_intr-when-enabling-guest_mod.patch b/meta-snowyowl/recipes-kernel/linux/files/0188-iommu-amd-Enable-ga_log_intr-when-enabling-guest_mod.patch new file mode 100755 index 00000000..f39df00d --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0188-iommu-amd-Enable-ga_log_intr-when-enabling-guest_mod.patch @@ -0,0 +1,37 @@ +From 91b5a0c0fb7ffdfd726ec048649b499d310708d9 Mon Sep 17 00:00:00 2001 +From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> +Date: Wed, 5 Jul 2017 21:29:59 -0500 +Subject: [PATCH 061/331] iommu/amd: Enable ga_log_intr when enabling + guest_mode + +commit efe6f241602cb61466895f6816b8ea6b90f04d4e upstream. + +IRTE[GALogIntr] bit should set when enabling guest_mode, which enables +IOMMU to generate entry in GALog when IRTE[IsRun] is not set, and send +an interrupt to notify IOMMU driver. + +Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> +Cc: Joerg Roedel <jroedel@suse.de> +Fixes: d98de49a53e48 ('iommu/amd: Enable vAPIC interrupt remapping mode by default') +Signed-off-by: Joerg Roedel <jroedel@suse.de> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/iommu/amd_iommu.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c +index 41800b6..c380b7e 100644 +--- a/drivers/iommu/amd_iommu.c ++++ b/drivers/iommu/amd_iommu.c +@@ -4294,6 +4294,7 @@ static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) + /* Setting */ + irte->hi.fields.ga_root_ptr = (pi_data->base >> 12); + irte->hi.fields.vector = vcpu_pi_info->vector; ++ irte->lo.fields_vapic.ga_log_intr = 1; + irte->lo.fields_vapic.guest_mode = 1; + irte->lo.fields_vapic.ga_tag = pi_data->ga_tag; + +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0189-iommu-amd-Finish-TLB-flush-in-amd_iommu_unmap.patch b/meta-snowyowl/recipes-kernel/linux/files/0189-iommu-amd-Finish-TLB-flush-in-amd_iommu_unmap.patch new file mode 100755 index 00000000..f9ec60c1 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0189-iommu-amd-Finish-TLB-flush-in-amd_iommu_unmap.patch @@ -0,0 +1,34 @@ +From cda810e9b68656102c4d12c4016b9ea76e45604d Mon Sep 17 00:00:00 2001 +From: Joerg Roedel <jroedel@suse.de> +Date: Fri, 13 Oct 2017 14:32:37 +0200 +Subject: [PATCH 086/331] iommu/amd: Finish TLB flush in amd_iommu_unmap() + +commit ce76353f169a6471542d999baf3d29b121dce9c0 upstream. + +The function only sends the flush command to the IOMMU(s), +but does not wait for its completion when it returns. Fix +that. + +Fixes: 601367d76bd1 ('x86/amd-iommu: Remove iommu_flush_domain function') +Signed-off-by: Joerg Roedel <jroedel@suse.de> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/iommu/amd_iommu.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c +index c380b7e..1a0b110 100644 +--- a/drivers/iommu/amd_iommu.c ++++ b/drivers/iommu/amd_iommu.c +@@ -3120,6 +3120,7 @@ static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova, + mutex_unlock(&domain->api_lock); + + domain_flush_tlb_pde(domain); ++ domain_flush_complete(domain); + + return unmap_size; + } +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0190-iommu-amd-Limit-the-IOVA-page-range-to-the-specified.patch b/meta-snowyowl/recipes-kernel/linux/files/0190-iommu-amd-Limit-the-IOVA-page-range-to-the-specified.patch new file mode 100755 index 00000000..9cc8e243 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0190-iommu-amd-Limit-the-IOVA-page-range-to-the-specified.patch @@ -0,0 +1,38 @@ +From 4e6907cae5feafc672ab00bab42fbf05e646496a Mon Sep 17 00:00:00 2001 +From: Gary R Hook <gary.hook@amd.com> +Date: Fri, 3 Nov 2017 10:50:34 -0600 +Subject: [PATCH 098/331] iommu/amd: Limit the IOVA page range to the specified + addresses + +[ Upstream commit b92b4fb5c14257c0e7eae291ecc1f7b1962e1699 ] + +The extent of pages specified when applying a reserved region should +include up to the last page of the range, but not the page following +the range. + +Signed-off-by: Gary R Hook <gary.hook@amd.com> +Fixes: 8d54d6c8b8f3 ('iommu/amd: Implement apply_dm_region call-back') +Signed-off-by: Alex Williamson <alex.williamson@redhat.com> +Signed-off-by: Sasha Levin <alexander.levin@verizon.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + drivers/iommu/amd_iommu.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c +index 1a0b110..0c910a8 100644 +--- a/drivers/iommu/amd_iommu.c ++++ b/drivers/iommu/amd_iommu.c +@@ -3211,7 +3211,7 @@ static void amd_iommu_apply_dm_region(struct device *dev, + unsigned long start, end; + + start = IOVA_PFN(region->start); +- end = IOVA_PFN(region->start + region->length); ++ end = IOVA_PFN(region->start + region->length - 1); + + WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL); + } +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0483-x86-mce-AMD-Give-a-name-to-MCA-bank-3-when-accessed-.patch b/meta-snowyowl/recipes-kernel/linux/files/0483-x86-mce-AMD-Give-a-name-to-MCA-bank-3-when-accessed-.patch new file mode 100644 index 00000000..24803219 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0483-x86-mce-AMD-Give-a-name-to-MCA-bank-3-when-accessed-.patch @@ -0,0 +1,54 @@ +From d521c1d4299aa6940c566aae6b5101e756612c4b Mon Sep 17 00:00:00 2001 +From: Yazen Ghannam <yazen.ghannam@amd.com> +Date: Thu, 30 Mar 2017 13:17:14 +0200 +Subject: [PATCH 03/10] x86/mce/AMD: Give a name to MCA bank 3 when accessed + with legacy MSRs + +MCA bank 3 is reserved on systems pre-Fam17h, so it didn't have a name. +However, MCA bank 3 is defined on Fam17h systems and can be accessed +using legacy MSRs. Without a name we get a stack trace on Fam17h systems +when trying to register sysfs files for bank 3 on kernels that don't +recognize Scalable MCA. + +Call MCA bank 3 "decode_unit" since this is what it represents on +Fam17h. This will allow kernels without SMCA support to see this bank on +Fam17h+ and prevent the stack trace. This will not affect older systems +since this bank is reserved on them, i.e. it'll be ignored. + +Tested on AMD Fam15h and Fam17h systems. + + WARNING: CPU: 26 PID: 1 at lib/kobject.c:210 kobject_add_internal + kobject: (ffff88085bb256c0): attempted to be registered with empty name! + ... + Call Trace: + kobject_add_internal + kobject_add + kobject_create_and_add + threshold_create_device + threshold_init_device + +Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> +Signed-off-by: Borislav Petkov <bp@suse.de> +Link: http://lkml.kernel.org/r/1490102285-3659-1-git-send-email-Yazen.Ghannam@amd.com +Signed-off-by: Thomas Gleixner <tglx@linutronix.de> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + arch/x86/kernel/cpu/mcheck/mce_amd.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c +index 48e875d..ea553db 100644 +--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c ++++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c +@@ -61,7 +61,7 @@ static const char * const th_names[] = { + "load_store", + "insn_fetch", + "combined_unit", +- "", ++ "decode_unit", + "northbridge", + "execution_unit", + }; +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0484-x86-mce-Convert-threshold_bank.cpus-from-atomic_t-to.patch b/meta-snowyowl/recipes-kernel/linux/files/0484-x86-mce-Convert-threshold_bank.cpus-from-atomic_t-to.patch new file mode 100644 index 00000000..e2105e53 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0484-x86-mce-Convert-threshold_bank.cpus-from-atomic_t-to.patch @@ -0,0 +1,82 @@ +From eaf03de61d40ddf14876380f644446e7921340a9 Mon Sep 17 00:00:00 2001 +From: Elena Reshetova <elena.reshetova@intel.com> +Date: Fri, 19 May 2017 11:39:13 +0200 +Subject: [PATCH 04/10] x86/mce: Convert threshold_bank.cpus from atomic_t to + refcount_t + +The refcount_t type and corresponding API should be used instead +of atomic_t when the variable is used as a reference counter. This +allows to avoid accidental refcounter overflows that might lead to +use-after-free situations. + +Suggested-by: Kees Cook <keescook@chromium.org> +Signed-off-by: Elena Reshetova <elena.reshetova@intel.com> +Signed-off-by: Borislav Petkov <bp@suse.de> +Reviewed-by: Hans Liljestrand <ishkamiel@gmail.com> +Reviewed-by: David Windsor <dwindsor@gmail.com> +Cc: Tony Luck <tony.luck@intel.com> +Cc: Yazen Ghannam <Yazen.Ghannam@amd.com> +Cc: linux-edac <linux-edac@vger.kernel.org> +Link: http://lkml.kernel.org/r/1492695536-5947-1-git-send-email-elena.reshetova@intel.com +Signed-off-by: Thomas Gleixner <tglx@linutronix.de> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + arch/x86/include/asm/amd_nb.h | 3 ++- + arch/x86/kernel/cpu/mcheck/mce_amd.c | 6 +++--- + 2 files changed, 5 insertions(+), 4 deletions(-) + +diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h +index 00c88a0..da181ad 100644 +--- a/arch/x86/include/asm/amd_nb.h ++++ b/arch/x86/include/asm/amd_nb.h +@@ -3,6 +3,7 @@ + + #include <linux/ioport.h> + #include <linux/pci.h> ++#include <linux/refcount.h> + + struct amd_nb_bus_dev_range { + u8 bus; +@@ -55,7 +56,7 @@ struct threshold_bank { + struct threshold_block *blocks; + + /* initialized to the number of CPUs on the node sharing this bank */ +- atomic_t cpus; ++ refcount_t cpus; + }; + + struct amd_northbridge { +diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c +index ea553db..b5b352c 100644 +--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c ++++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c +@@ -1203,7 +1203,7 @@ static int threshold_create_bank(unsigned int cpu, unsigned int bank) + goto out; + + per_cpu(threshold_banks, cpu)[bank] = b; +- atomic_inc(&b->cpus); ++ refcount_inc(&b->cpus); + + err = __threshold_add_blocks(b); + +@@ -1226,7 +1226,7 @@ static int threshold_create_bank(unsigned int cpu, unsigned int bank) + per_cpu(threshold_banks, cpu)[bank] = b; + + if (is_shared_bank(bank)) { +- atomic_set(&b->cpus, 1); ++ refcount_set(&b->cpus, 1); + + /* nb is already initialized, see above */ + if (nb) { +@@ -1290,7 +1290,7 @@ static void threshold_remove_bank(unsigned int cpu, int bank) + goto free_out; + + if (is_shared_bank(bank)) { +- if (!atomic_dec_and_test(&b->cpus)) { ++ if (!refcount_dec_and_test(&b->cpus)) { + __threshold_remove_blocks(b); + per_cpu(threshold_banks, cpu)[bank] = NULL; + return; +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0485-x86-mce-AMD-Redo-error-logging-from-APIC-LVT-interru.patch b/meta-snowyowl/recipes-kernel/linux/files/0485-x86-mce-AMD-Redo-error-logging-from-APIC-LVT-interru.patch new file mode 100644 index 00000000..377801f5 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0485-x86-mce-AMD-Redo-error-logging-from-APIC-LVT-interru.patch @@ -0,0 +1,253 @@ +From 448e70854e4578b043f3229e463076b5406141ba Mon Sep 17 00:00:00 2001 +From: Yazen Ghannam <yazen.ghannam@amd.com> +Date: Fri, 19 May 2017 11:39:14 +0200 +Subject: [PATCH 05/10] x86/mce/AMD: Redo error logging from APIC LVT interrupt + handlers + +We have support for the new SMCA MCA_DE{STAT,ADDR} registers in Linux. +So we've used these registers in place of MCA_{STATUS,ADDR} on SMCA +systems. + +However, the guidance for current SMCA implementations of is to continue +using MCA_{STATUS,ADDR} and to use MCA_DE{STAT,ADDR} only if a Deferred +error was not found in the former registers. If we logged a Deferred +error in MCA_STATUS then we should also clear MCA_DESTAT. This also +means we shouldn't clear MCA_CONFIG[LogDeferredInMcaStat]. + +Rework __log_error() to only log an error and add helpers for the +different error types being logged from the corresponding interrupt +handlers. + +Boris: carve out common functionality into a _log_error_bank(). Cleanup +comments, check MCi_STATUS bits before reading MSRs. Streamline flow. + +Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> +Signed-off-by: Borislav Petkov <bp@suse.de> +Cc: Tony Luck <tony.luck@intel.com> +Cc: linux-edac <linux-edac@vger.kernel.org> +Link: http://lkml.kernel.org/r/1493147772-2721-1-git-send-email-Yazen.Ghannam@amd.com +Signed-off-by: Thomas Gleixner <tglx@linutronix.de> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + arch/x86/kernel/cpu/mcheck/mce_amd.c | 147 ++++++++++++++++++----------------- + 1 file changed, 74 insertions(+), 73 deletions(-) + +diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c +index b5b352c..58e4cea 100644 +--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c ++++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c +@@ -473,20 +473,6 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, + smca_high |= BIT(0); + + /* +- * SMCA logs Deferred Error information in MCA_DE{STAT,ADDR} +- * registers with the option of additionally logging to +- * MCA_{STATUS,ADDR} if MCA_CONFIG[LogDeferredInMcaStat] is set. +- * +- * This bit is usually set by BIOS to retain the old behavior +- * for OSes that don't use the new registers. Linux supports the +- * new registers so let's disable that additional logging here. +- * +- * MCA_CONFIG[LogDeferredInMcaStat] is bit 34 (bit 2 in the high +- * portion of the MSR). +- */ +- smca_high &= ~BIT(2); +- +- /* + * SMCA sets the Deferred Error Interrupt type per bank. + * + * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us +@@ -756,37 +742,19 @@ int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) + } + EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr); + +-static void +-__log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc) ++static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc) + { +- u32 msr_status = msr_ops.status(bank); +- u32 msr_addr = msr_ops.addr(bank); + struct mce m; +- u64 status; +- +- WARN_ON_ONCE(deferred_err && threshold_err); +- +- if (deferred_err && mce_flags.smca) { +- msr_status = MSR_AMD64_SMCA_MCx_DESTAT(bank); +- msr_addr = MSR_AMD64_SMCA_MCx_DEADDR(bank); +- } +- +- rdmsrl(msr_status, status); +- +- if (!(status & MCI_STATUS_VAL)) +- return; + + mce_setup(&m); + + m.status = status; ++ m.misc = misc; + m.bank = bank; + m.tsc = rdtsc(); + +- if (threshold_err) +- m.misc = misc; +- + if (m.status & MCI_STATUS_ADDRV) { +- rdmsrl(msr_addr, m.addr); ++ m.addr = addr; + + /* + * Extract [55:<lsb>] where lsb is the least significant +@@ -807,8 +775,6 @@ __log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc) + } + + mce_log(&m); +- +- wrmsrl(msr_status, 0); + } + + static inline void __smp_deferred_error_interrupt(void) +@@ -833,45 +799,85 @@ asmlinkage __visible void smp_trace_deferred_error_interrupt(void) + exiting_ack_irq(); + } + +-/* APIC interrupt handler for deferred errors */ +-static void amd_deferred_error_interrupt(void) ++/* ++ * Returns true if the logged error is deferred. False, otherwise. ++ */ ++static inline bool ++_log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) + { +- unsigned int bank; +- u32 msr_status; +- u64 status; ++ u64 status, addr = 0; + +- for (bank = 0; bank < mca_cfg.banks; ++bank) { +- msr_status = (mce_flags.smca) ? MSR_AMD64_SMCA_MCx_DESTAT(bank) +- : msr_ops.status(bank); ++ rdmsrl(msr_stat, status); ++ if (!(status & MCI_STATUS_VAL)) ++ return false; + +- rdmsrl(msr_status, status); ++ if (status & MCI_STATUS_ADDRV) ++ rdmsrl(msr_addr, addr); + +- if (!(status & MCI_STATUS_VAL) || +- !(status & MCI_STATUS_DEFERRED)) +- continue; ++ __log_error(bank, status, addr, misc); + +- __log_error(bank, true, false, 0); +- break; +- } ++ wrmsrl(status, 0); ++ ++ return status & MCI_STATUS_DEFERRED; + } + + /* +- * APIC Interrupt Handler ++ * We have three scenarios for checking for Deferred errors: ++ * ++ * 1) Non-SMCA systems check MCA_STATUS and log error if found. ++ * 2) SMCA systems check MCA_STATUS. If error is found then log it and also ++ * clear MCA_DESTAT. ++ * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and ++ * log it. + */ ++static void log_error_deferred(unsigned int bank) ++{ ++ bool defrd; ++ ++ defrd = _log_error_bank(bank, msr_ops.status(bank), ++ msr_ops.addr(bank), 0); ++ ++ if (!mce_flags.smca) ++ return; ++ ++ /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */ ++ if (defrd) { ++ wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0); ++ return; ++ } ++ ++ /* ++ * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check ++ * for a valid error. ++ */ ++ _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank), ++ MSR_AMD64_SMCA_MCx_DEADDR(bank), 0); ++} ++ ++/* APIC interrupt handler for deferred errors */ ++static void amd_deferred_error_interrupt(void) ++{ ++ unsigned int bank; ++ ++ for (bank = 0; bank < mca_cfg.banks; ++bank) ++ log_error_deferred(bank); ++} ++ ++static void log_error_thresholding(unsigned int bank, u64 misc) ++{ ++ _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc); ++} + + /* +- * threshold interrupt handler will service THRESHOLD_APIC_VECTOR. +- * the interrupt goes off when error_count reaches threshold_limit. +- * the handler will simply log mcelog w/ software defined bank number. ++ * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt ++ * goes off when error_count reaches threshold_limit. + */ +- + static void amd_threshold_interrupt(void) + { + u32 low = 0, high = 0, address = 0; + unsigned int bank, block, cpu = smp_processor_id(); + struct thresh_restart tr; + +- /* assume first bank caused it */ + for (bank = 0; bank < mca_cfg.banks; ++bank) { + if (!(per_cpu(bank_map, cpu) & (1 << bank))) + continue; +@@ -894,23 +900,18 @@ static void amd_threshold_interrupt(void) + (high & MASK_LOCKED_HI)) + continue; + +- /* +- * Log the machine check that caused the threshold +- * event. +- */ +- if (high & MASK_OVERFLOW_HI) +- goto log; +- } +- } +- return; ++ if (!(high & MASK_OVERFLOW_HI)) ++ continue; + +-log: +- __log_error(bank, false, true, ((u64)high << 32) | low); ++ /* Log the MCE which caused the threshold event. */ ++ log_error_thresholding(bank, ((u64)high << 32) | low); + +- /* Reset threshold block after logging error. */ +- memset(&tr, 0, sizeof(tr)); +- tr.b = &per_cpu(threshold_banks, cpu)[bank]->blocks[block]; +- threshold_restart_bank(&tr); ++ /* Reset threshold block after logging error. */ ++ memset(&tr, 0, sizeof(tr)); ++ tr.b = &per_cpu(threshold_banks, cpu)[bank]->blocks[block]; ++ threshold_restart_bank(&tr); ++ } ++ } + } + + /* +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0486-x86-mce-AMD-Carve-out-SMCA-bank-configuration.patch b/meta-snowyowl/recipes-kernel/linux/files/0486-x86-mce-AMD-Carve-out-SMCA-bank-configuration.patch new file mode 100644 index 00000000..523aece8 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0486-x86-mce-AMD-Carve-out-SMCA-bank-configuration.patch @@ -0,0 +1,147 @@ +From 5514f9a6ffc52bf263afc57171037ed7ec5033fa Mon Sep 17 00:00:00 2001 +From: Yazen Ghannam <yazen.ghannam@amd.com> +Date: Fri, 19 May 2017 11:39:15 +0200 +Subject: [PATCH 06/10] x86/mce/AMD: Carve out SMCA bank configuration + +Scalable MCA systems have a new MCA_CONFIG register that we use to +configure each bank. We currently use this when we set up thresholding. +However, this is logically separate. + +Group all SMCA-related initialization into a single function. + +Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> +Signed-off-by: Borislav Petkov <bp@suse.de> +Cc: Tony Luck <tony.luck@intel.com> +Cc: linux-edac <linux-edac@vger.kernel.org> +Link: http://lkml.kernel.org/r/1493147772-2721-2-git-send-email-Yazen.Ghannam@amd.com +Signed-off-by: Thomas Gleixner <tglx@linutronix.de> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + arch/x86/kernel/cpu/mcheck/mce_amd.c | 76 ++++++++++++++++++------------------ + 1 file changed, 38 insertions(+), 38 deletions(-) + +diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c +index 58e4cea..82d0c1c 100644 +--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c ++++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c +@@ -165,17 +165,48 @@ static void default_deferred_error_interrupt(void) + } + void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; + +-static void get_smca_bank_info(unsigned int bank) ++static void smca_configure(unsigned int bank, unsigned int cpu) + { +- unsigned int i, hwid_mcatype, cpu = smp_processor_id(); ++ unsigned int i, hwid_mcatype; + struct smca_hwid *s_hwid; +- u32 high, instance_id; ++ u32 high, low; ++ u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank); ++ ++ /* Set appropriate bits in MCA_CONFIG */ ++ if (!rdmsr_safe(smca_config, &low, &high)) { ++ /* ++ * OS is required to set the MCAX bit to acknowledge that it is ++ * now using the new MSR ranges and new registers under each ++ * bank. It also means that the OS will configure deferred ++ * errors in the new MCx_CONFIG register. If the bit is not set, ++ * uncorrectable errors will cause a system panic. ++ * ++ * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) ++ */ ++ high |= BIT(0); ++ ++ /* ++ * SMCA sets the Deferred Error Interrupt type per bank. ++ * ++ * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us ++ * if the DeferredIntType bit field is available. ++ * ++ * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the ++ * high portion of the MSR). OS should set this to 0x1 to enable ++ * APIC based interrupt. First, check that no interrupt has been ++ * set. ++ */ ++ if ((low & BIT(5)) && !((high >> 5) & 0x3)) ++ high |= BIT(5); ++ ++ wrmsr(smca_config, low, high); ++ } + + /* Collect bank_info using CPU 0 for now. */ + if (cpu) + return; + +- if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &instance_id, &high)) { ++ if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { + pr_warn("Failed to read MCA_IPID for bank %d\n", bank); + return; + } +@@ -192,7 +223,7 @@ static void get_smca_bank_info(unsigned int bank) + smca_get_name(s_hwid->bank_type)); + + smca_banks[bank].hwid = s_hwid; +- smca_banks[bank].id = instance_id; ++ smca_banks[bank].id = low; + smca_banks[bank].sysfs_id = s_hwid->count++; + break; + } +@@ -434,7 +465,7 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, + int offset, u32 misc_high) + { + unsigned int cpu = smp_processor_id(); +- u32 smca_low, smca_high, smca_addr; ++ u32 smca_low, smca_high; + struct threshold_block b; + int new; + +@@ -458,37 +489,6 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, + goto set_offset; + } + +- smca_addr = MSR_AMD64_SMCA_MCx_CONFIG(bank); +- +- if (!rdmsr_safe(smca_addr, &smca_low, &smca_high)) { +- /* +- * OS is required to set the MCAX bit to acknowledge that it is +- * now using the new MSR ranges and new registers under each +- * bank. It also means that the OS will configure deferred +- * errors in the new MCx_CONFIG register. If the bit is not set, +- * uncorrectable errors will cause a system panic. +- * +- * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) +- */ +- smca_high |= BIT(0); +- +- /* +- * SMCA sets the Deferred Error Interrupt type per bank. +- * +- * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us +- * if the DeferredIntType bit field is available. +- * +- * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the +- * high portion of the MSR). OS should set this to 0x1 to enable +- * APIC based interrupt. First, check that no interrupt has been +- * set. +- */ +- if ((smca_low & BIT(5)) && !((smca_high >> 5) & 0x3)) +- smca_high |= BIT(5); +- +- wrmsr(smca_addr, smca_low, smca_high); +- } +- + /* Gather LVT offset for thresholding: */ + if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high)) + goto out; +@@ -517,7 +517,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) + + for (bank = 0; bank < mca_cfg.banks; ++bank) { + if (mce_flags.smca) +- get_smca_bank_info(bank); ++ smca_configure(bank, cpu); + + for (block = 0; block < NR_BLOCKS; ++block) { + address = get_block_address(cpu, address, low, high, bank, block); +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0487-x86-mce-AMD-Use-msr_stat-when-clearing-MCA_STATUS.patch b/meta-snowyowl/recipes-kernel/linux/files/0487-x86-mce-AMD-Use-msr_stat-when-clearing-MCA_STATUS.patch new file mode 100644 index 00000000..3bc5cb8c --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0487-x86-mce-AMD-Use-msr_stat-when-clearing-MCA_STATUS.patch @@ -0,0 +1,49 @@ +From 66004d7800e0310fac27a01e4139cb0c798e3c8d Mon Sep 17 00:00:00 2001 +From: Yazen Ghannam <yazen.ghannam@amd.com> +Date: Tue, 13 Jun 2017 18:28:28 +0200 +Subject: [PATCH 07/10] x86/mce/AMD: Use msr_stat when clearing MCA_STATUS + +The value of MCA_STATUS is used as the MSR when clearing MCA_STATUS. + +This may cause the following warning: + + unchecked MSR access error: WRMSR to 0x11b (tried to write 0x0000000000000000) + Call Trace: + <IRQ> + smp_threshold_interrupt() + threshold_interrupt() + +Use msr_stat instead which has the MSR address. + +Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> +Signed-off-by: Borislav Petkov <bp@suse.de> +Cc: Borislav Petkov <bp@alien8.de> +Cc: Linus Torvalds <torvalds@linux-foundation.org> +Cc: Peter Zijlstra <peterz@infradead.org> +Cc: Thomas Gleixner <tglx@linutronix.de> +Cc: Tony Luck <tony.luck@intel.com> +Cc: linux-edac <linux-edac@vger.kernel.org> +Fixes: 37d43acfd79f ("x86/mce/AMD: Redo error logging from APIC LVT interrupt handlers") +Link: http://lkml.kernel.org/r/20170613162835.30750-2-bp@alien8.de +Signed-off-by: Ingo Molnar <mingo@kernel.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + arch/x86/kernel/cpu/mcheck/mce_amd.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c +index 82d0c1c..a4e38c4 100644 +--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c ++++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c +@@ -816,7 +816,7 @@ _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc) + + __log_error(bank, status, addr, misc); + +- wrmsrl(status, 0); ++ wrmsrl(msr_stat, 0); + + return status & MCI_STATUS_DEFERRED; + } +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0488-x86-mce-AMD-Use-saved-threshold-block-info-in-interr.patch b/meta-snowyowl/recipes-kernel/linux/files/0488-x86-mce-AMD-Use-saved-threshold-block-info-in-interr.patch new file mode 100644 index 00000000..396ea4a5 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0488-x86-mce-AMD-Use-saved-threshold-block-info-in-interr.patch @@ -0,0 +1,143 @@ +From 6fbcc132ec02586165b39b6a324becedc1da052f Mon Sep 17 00:00:00 2001 +From: Yazen Ghannam <yazen.ghannam@amd.com> +Date: Tue, 13 Jun 2017 18:28:29 +0200 +Subject: [PATCH 08/10] x86/mce/AMD: Use saved threshold block info in + interrupt handler + +In the amd_threshold_interrupt() handler, we loop through every possible +block in each bank and rediscover the block's address and if it's valid, +e.g. valid, counter present and not locked. + +However, we already have the address saved in the threshold blocks list +for each CPU and bank. The list only contains blocks that have passed +all the valid checks. + +Besides the redundancy, there's also a smp_call_function* in +get_block_address() which causes a warning when servicing the interrupt: + + WARNING: CPU: 0 PID: 0 at kernel/smp.c:281 smp_call_function_single+0xdd/0xf0 + ... + Call Trace: + <IRQ> + rdmsr_safe_on_cpu() + get_block_address.isra.2() + amd_threshold_interrupt() + smp_threshold_interrupt() + threshold_interrupt() + +because we do get called in an interrupt handler *with* interrupts +disabled, which can result in a deadlock. + +Drop the redundant valid checks and move the overflow check, logging and +block reset into a separate function. + +Check the first block then iterate over the rest. This procedure is +needed since the first block is used as the head of the list. + +Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> +Signed-off-by: Borislav Petkov <bp@suse.de> +Cc: Borislav Petkov <bp@alien8.de> +Cc: Linus Torvalds <torvalds@linux-foundation.org> +Cc: Peter Zijlstra <peterz@infradead.org> +Cc: Thomas Gleixner <tglx@linutronix.de> +Cc: Tony Luck <tony.luck@intel.com> +Cc: linux-edac <linux-edac@vger.kernel.org> +Link: http://lkml.kernel.org/r/20170613162835.30750-3-bp@alien8.de +Signed-off-by: Ingo Molnar <mingo@kernel.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + arch/x86/kernel/cpu/mcheck/mce_amd.c | 66 +++++++++++++++++++----------------- + 1 file changed, 35 insertions(+), 31 deletions(-) + +diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c +index a4e38c4..188f95b 100644 +--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c ++++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c +@@ -868,49 +868,53 @@ static void log_error_thresholding(unsigned int bank, u64 misc) + _log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc); + } + ++static void log_and_reset_block(struct threshold_block *block) ++{ ++ struct thresh_restart tr; ++ u32 low = 0, high = 0; ++ ++ if (!block) ++ return; ++ ++ if (rdmsr_safe(block->address, &low, &high)) ++ return; ++ ++ if (!(high & MASK_OVERFLOW_HI)) ++ return; ++ ++ /* Log the MCE which caused the threshold event. */ ++ log_error_thresholding(block->bank, ((u64)high << 32) | low); ++ ++ /* Reset threshold block after logging error. */ ++ memset(&tr, 0, sizeof(tr)); ++ tr.b = block; ++ threshold_restart_bank(&tr); ++} ++ + /* + * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt + * goes off when error_count reaches threshold_limit. + */ + static void amd_threshold_interrupt(void) + { +- u32 low = 0, high = 0, address = 0; +- unsigned int bank, block, cpu = smp_processor_id(); +- struct thresh_restart tr; ++ struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL; ++ unsigned int bank, cpu = smp_processor_id(); + + for (bank = 0; bank < mca_cfg.banks; ++bank) { + if (!(per_cpu(bank_map, cpu) & (1 << bank))) + continue; +- for (block = 0; block < NR_BLOCKS; ++block) { +- address = get_block_address(cpu, address, low, high, bank, block); +- if (!address) +- break; +- +- if (rdmsr_safe(address, &low, &high)) +- break; +- +- if (!(high & MASK_VALID_HI)) { +- if (block) +- continue; +- else +- break; +- } +- +- if (!(high & MASK_CNTP_HI) || +- (high & MASK_LOCKED_HI)) +- continue; +- +- if (!(high & MASK_OVERFLOW_HI)) +- continue; + +- /* Log the MCE which caused the threshold event. */ +- log_error_thresholding(bank, ((u64)high << 32) | low); ++ first_block = per_cpu(threshold_banks, cpu)[bank]->blocks; ++ if (!first_block) ++ continue; + +- /* Reset threshold block after logging error. */ +- memset(&tr, 0, sizeof(tr)); +- tr.b = &per_cpu(threshold_banks, cpu)[bank]->blocks[block]; +- threshold_restart_bank(&tr); +- } ++ /* ++ * The first block is also the head of the list. Check it first ++ * before iterating over the rest. ++ */ ++ log_and_reset_block(first_block); ++ list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj) ++ log_and_reset_block(block); + } + } + +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0489-x86-mce-AMD-Allow-any-CPU-to-initialize-the-smca_ban.patch b/meta-snowyowl/recipes-kernel/linux/files/0489-x86-mce-AMD-Allow-any-CPU-to-initialize-the-smca_ban.patch new file mode 100644 index 00000000..86ef24f9 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0489-x86-mce-AMD-Allow-any-CPU-to-initialize-the-smca_ban.patch @@ -0,0 +1,77 @@ +From 5882e0374c595e107cd3d899ed9072f3af32f578 Mon Sep 17 00:00:00 2001 +From: Yazen Ghannam <yazen.ghannam@amd.com> +Date: Mon, 24 Jul 2017 12:12:28 +0200 +Subject: [PATCH 09/10] x86/mce/AMD: Allow any CPU to initialize the smca_banks + array + +Current SMCA implementations have the same banks on each CPU with the +non-core banks only visible to a "master thread" on each die. Practically, +this means the smca_banks array, which describes the banks, only needs to +be populated once by a single master thread. + +CPU 0 seemed like a good candidate to do the populating. However, it's +possible that CPU 0 is not enabled in which case the smca_banks array won't +be populated. + +Rather than try to figure out another master thread to do the populating, +we should just allow any CPU to populate the array. + +Drop the CPU 0 check and return early if the bank was already initialized. +Also, drop the WARNing about an already initialized bank, since this will +be a common, expected occurrence. + +The smca_banks array is only populated at boot time and CPUs are brought +online sequentially. So there's no need for locking around the array. + +If the first CPU up is a master thread, then it will populate the array +with all banks, core and non-core. Every CPU afterwards will return +early. If the first CPU up is not a master thread, then it will populate +the array with all core banks. The first CPU afterwards that is a master +thread will skip populating the core banks and continue populating the +non-core banks. + +Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> +Signed-off-by: Borislav Petkov <bp@suse.de> +Acked-by: Jack Miller <jack@codezen.org> +Cc: Linus Torvalds <torvalds@linux-foundation.org> +Cc: Peter Zijlstra <peterz@infradead.org> +Cc: Thomas Gleixner <tglx@linutronix.de> +Cc: Tony Luck <tony.luck@intel.com> +Cc: linux-edac <linux-edac@vger.kernel.org> +Link: http://lkml.kernel.org/r/20170724101228.17326-4-bp@alien8.de +Signed-off-by: Ingo Molnar <mingo@kernel.org> +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + arch/x86/kernel/cpu/mcheck/mce_amd.c | 9 ++------- + 1 file changed, 2 insertions(+), 7 deletions(-) + +diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c +index 188f95b..e08d323 100644 +--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c ++++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c +@@ -202,8 +202,8 @@ static void smca_configure(unsigned int bank, unsigned int cpu) + wrmsr(smca_config, low, high); + } + +- /* Collect bank_info using CPU 0 for now. */ +- if (cpu) ++ /* Return early if this bank was already initialized. */ ++ if (smca_banks[bank].hwid) + return; + + if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { +@@ -217,11 +217,6 @@ static void smca_configure(unsigned int bank, unsigned int cpu) + for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { + s_hwid = &smca_hwid_mcatypes[i]; + if (hwid_mcatype == s_hwid->hwid_mcatype) { +- +- WARN(smca_banks[bank].hwid, +- "Bank %s already initialized!\n", +- smca_get_name(s_hwid->bank_type)); +- + smca_banks[bank].hwid = s_hwid; + smca_banks[bank].id = low; + smca_banks[bank].sysfs_id = s_hwid->count++; +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/0490-Dependency-added.patch b/meta-snowyowl/recipes-kernel/linux/files/0490-Dependency-added.patch new file mode 100644 index 00000000..41ff7843 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/linux/files/0490-Dependency-added.patch @@ -0,0 +1,122 @@ +From e3fab5d128f3000c67b450d55215fd9f0861cd2d Mon Sep 17 00:00:00 2001 +From: Sudheesh Mavila <sudheesh.mavila@amd.com> +Date: Fri, 25 May 2018 16:05:11 +0530 +Subject: [PATCH 10/10] Dependency added + +Signed-off-by: Sudheesh Mavila <sudheesh.mavila@amd.com> +--- + include/linux/refcount.h | 102 +++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 102 insertions(+) + create mode 100755 include/linux/refcount.h + +diff --git a/include/linux/refcount.h b/include/linux/refcount.h +new file mode 100755 +index 0000000..4193c41 +--- /dev/null ++++ b/include/linux/refcount.h +@@ -0,0 +1,102 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++#ifndef _LINUX_REFCOUNT_H ++#define _LINUX_REFCOUNT_H ++ ++#include <linux/atomic.h> ++#include <linux/mutex.h> ++#include <linux/spinlock.h> ++#include <linux/kernel.h> ++ ++/** ++ * struct refcount_t - variant of atomic_t specialized for reference counts ++ * @refs: atomic_t counter field ++ * ++ * The counter saturates at UINT_MAX and will not move once ++ * there. This avoids wrapping the counter and causing 'spurious' ++ * use-after-free bugs. ++ */ ++typedef struct refcount_struct { ++ atomic_t refs; ++} refcount_t; ++ ++#define REFCOUNT_INIT(n) { .refs = ATOMIC_INIT(n), } ++ ++/** ++ * refcount_set - set a refcount's value ++ * @r: the refcount ++ * @n: value to which the refcount will be set ++ */ ++static inline void refcount_set(refcount_t *r, unsigned int n) ++{ ++ atomic_set(&r->refs, n); ++} ++ ++/** ++ * refcount_read - get a refcount's value ++ * @r: the refcount ++ * ++ * Return: the refcount's value ++ */ ++static inline unsigned int refcount_read(const refcount_t *r) ++{ ++ return atomic_read(&r->refs); ++} ++ ++#ifdef CONFIG_REFCOUNT_FULL ++extern __must_check bool refcount_add_not_zero(unsigned int i, refcount_t *r); ++extern void refcount_add(unsigned int i, refcount_t *r); ++ ++extern __must_check bool refcount_inc_not_zero(refcount_t *r); ++extern void refcount_inc(refcount_t *r); ++ ++extern __must_check bool refcount_sub_and_test(unsigned int i, refcount_t *r); ++ ++extern __must_check bool refcount_dec_and_test(refcount_t *r); ++extern void refcount_dec(refcount_t *r); ++#else ++# ifdef CONFIG_ARCH_HAS_REFCOUNT ++# include <asm/refcount.h> ++# else ++static inline __must_check bool refcount_add_not_zero(unsigned int i, refcount_t *r) ++{ ++ return atomic_add_unless(&r->refs, i, 0); ++} ++ ++static inline void refcount_add(unsigned int i, refcount_t *r) ++{ ++ atomic_add(i, &r->refs); ++} ++ ++static inline __must_check bool refcount_inc_not_zero(refcount_t *r) ++{ ++ return atomic_add_unless(&r->refs, 1, 0); ++} ++ ++static inline void refcount_inc(refcount_t *r) ++{ ++ atomic_inc(&r->refs); ++} ++ ++static inline __must_check bool refcount_sub_and_test(unsigned int i, refcount_t *r) ++{ ++ return atomic_sub_and_test(i, &r->refs); ++} ++ ++static inline __must_check bool refcount_dec_and_test(refcount_t *r) ++{ ++ return atomic_dec_and_test(&r->refs); ++} ++ ++static inline void refcount_dec(refcount_t *r) ++{ ++ atomic_dec(&r->refs); ++} ++# endif /* !CONFIG_ARCH_HAS_REFCOUNT */ ++#endif /* CONFIG_REFCOUNT_FULL */ ++ ++extern __must_check bool refcount_dec_if_one(refcount_t *r); ++extern __must_check bool refcount_dec_not_one(refcount_t *r); ++extern __must_check bool refcount_dec_and_mutex_lock(refcount_t *r, struct mutex *lock); ++extern __must_check bool refcount_dec_and_lock(refcount_t *r, spinlock_t *lock); ++ ++#endif /* _LINUX_REFCOUNT_H */ +-- +2.7.4 + diff --git a/meta-snowyowl/recipes-kernel/linux/files/snowyowl-user-patches.scc b/meta-snowyowl/recipes-kernel/linux/files/snowyowl-user-patches.scc index 9a3c1aed..75f4dd46 100755 --- a/meta-snowyowl/recipes-kernel/linux/files/snowyowl-user-patches.scc +++ b/meta-snowyowl/recipes-kernel/linux/files/snowyowl-user-patches.scc @@ -190,3 +190,37 @@ patch 0162-crypto-ccp-invoke-the-DMA-callback-in-a-standard-way.patch patch 0163-amd-xgbe-Add-pre-post-auto-negotiation-phy-hooks.patch patch 0164-amd-xgbe-Improve-KR-auto-negotiation-and-training.patch patch 0001-net-core-dev.c-fix-build-for-full-RT-kernel.patch +patch 0165-License-cleanup-add-SPDX-GPL-2.0-license-identifier-.patch +patch 0166-mm-remove-__GFP_COLD.patch +patch 0167-net-amd-xgbe-Get-rid-of-custom-hex_dump_to_buffer.patch +patch 0168-net-amd-xgbe-fix-comparison-to-bitshift-when-dealing.patch +patch 0169-amd-xgbe-Restore-PCI-interrupt-enablement-setting-on.patch +patch 0170-ethernet-Use-octal-not-symbolic-permissions.patch +patch 0171-amd-xgbe-Only-use-the-SFP-supported-transceiver-sign.patch +patch 0172-Modification-to-previous-commit-305f3ad05fec3a5f0d7b.patch +patch 0173-crypto-gcm-wait-for-crypto-op-not-signal-safe.patch +patch 0174-crypto-drbg-wait-for-crypto-op-not-signal-safe.patch +patch 0175-crypto-asymmetric_keys-handle-EBUSY-due-to-backlog-c.patch +patch 0176-crypto-Work-around-deallocated-stack-frame-reference.patch +patch 0177-crypto-drbg-Fixes-panic-in-wait_for_completion-call.patch +patch 0178-crypto-ccp-remove-unused-variable-qim.patch +patch 0179-crypto-ccp-use-ENOSPC-for-transient-busy-indication.patch +patch 0180-crypto-ccp-Build-the-AMD-secure-processor-driver-onl.patch +patch 0181-crypto-ccp-Add-Platform-Security-Processor-PSP-devic.patch +patch 0182-crypto-ccp-Define-SEV-userspace-ioctl-and-command-id.patch +patch 0183-mqueue-fix-a-use-after-free-in-sys_mq_notify.patch +patch 0184-i2c-designware-Fix-system-suspend.patch +patch 0185-iommu-dma-Don-t-reserve-PCI-I-O-windows.patch +patch 0186-iommu-amd-Fix-incorrect-error-handling-in-amd_iommu_.patch +patch 0187-iommu-amd-Fix-interrupt-remapping-when-disable-guest.patch +patch 0188-iommu-amd-Enable-ga_log_intr-when-enabling-guest_mod.patch +patch 0189-iommu-amd-Finish-TLB-flush-in-amd_iommu_unmap.patch +patch 0190-iommu-amd-Limit-the-IOVA-page-range-to-the-specified.patch +patch 0483-x86-mce-AMD-Give-a-name-to-MCA-bank-3-when-accessed-.patch +patch 0484-x86-mce-Convert-threshold_bank.cpus-from-atomic_t-to.patch +patch 0485-x86-mce-AMD-Redo-error-logging-from-APIC-LVT-interru.patch +patch 0486-x86-mce-AMD-Carve-out-SMCA-bank-configuration.patch +patch 0487-x86-mce-AMD-Use-msr_stat-when-clearing-MCA_STATUS.patch +patch 0488-x86-mce-AMD-Use-saved-threshold-block-info-in-interr.patch +patch 0489-x86-mce-AMD-Allow-any-CPU-to-initialize-the-smca_ban.patch +patch 0490-Dependency-added.patch diff --git a/meta-snowyowl/recipes-kernel/lttng/lttng-modules/0001-Update-kvm-instrumentation-for-4.15.patch b/meta-snowyowl/recipes-kernel/lttng/lttng-modules/0001-Update-kvm-instrumentation-for-4.15.patch new file mode 100644 index 00000000..3aa12e9c --- /dev/null +++ b/meta-snowyowl/recipes-kernel/lttng/lttng-modules/0001-Update-kvm-instrumentation-for-4.15.patch @@ -0,0 +1,49 @@ +From 37ab960eef4b96785906487cbb11bdf08a4e42b8 Mon Sep 17 00:00:00 2001 +From: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> +Date: Tue, 26 Dec 2017 09:47:22 -0500 +Subject: [PATCH 1/4] Update kvm instrumentation for 4.15 + +Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> +--- + instrumentation/events/lttng-module/kvm.h | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/instrumentation/events/lttng-module/kvm.h b/instrumentation/events/lttng-module/kvm.h +index a8b3e9a..c01772c 100644 +--- a/instrumentation/events/lttng-module/kvm.h ++++ b/instrumentation/events/lttng-module/kvm.h +@@ -84,6 +84,22 @@ LTTNG_TRACEPOINT_EVENT(kvm_ack_irq, + { KVM_TRACE_MMIO_READ, "read" }, \ + { KVM_TRACE_MMIO_WRITE, "write" } + ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,34)) ++ ++LTTNG_TRACEPOINT_EVENT(kvm_mmio, ++ TP_PROTO(int type, int len, u64 gpa, void *val), ++ TP_ARGS(type, len, gpa, val), ++ ++ TP_FIELDS( ++ ctf_integer(u32, type, type) ++ ctf_integer(u32, len, len) ++ ctf_integer(u64, gpa, gpa) ++ ctf_sequence_hex(unsigned char, val, val, u32, len) ++ ) ++) ++ ++#else /* #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,15,0)) */ ++ + LTTNG_TRACEPOINT_EVENT(kvm_mmio, + TP_PROTO(int type, int len, u64 gpa, u64 val), + TP_ARGS(type, len, gpa, val), +@@ -96,6 +112,8 @@ LTTNG_TRACEPOINT_EVENT(kvm_mmio, + ) + ) + ++#endif /* #else #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,15,0)) */ ++ + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,34)) + + #define kvm_fpu_load_symbol \ +-- +2.11.1 + diff --git a/meta-snowyowl/recipes-kernel/lttng/lttng-modules/0001-kvm.h-workaround-kernel-version-issues.patch b/meta-snowyowl/recipes-kernel/lttng/lttng-modules/0001-kvm.h-workaround-kernel-version-issues.patch new file mode 100644 index 00000000..9da99e6d --- /dev/null +++ b/meta-snowyowl/recipes-kernel/lttng/lttng-modules/0001-kvm.h-workaround-kernel-version-issues.patch @@ -0,0 +1,32 @@ +From 7bee7691eec41aa0d3697466250be7680a5e963d Mon Sep 17 00:00:00 2001 +From: Awais Belal <awais_belal@mentor.com> +Date: Thu, 14 Jun 2018 16:43:28 +0500 +Subject: [PATCH] kvm.h: workaround kernel version issues + +The kernel version for this change is different than +what we currently have for the AMD BSPs as there are +various patches backported for the kernel that make +this change otherwise irrelevant. Fix this by forcing +a known version that works. + +Signed-off-by: Awais Belal <awais_belal@mentor.com> +--- + instrumentation/events/lttng-module/kvm.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/instrumentation/events/lttng-module/kvm.h b/instrumentation/events/lttng-module/kvm.h +index 698cc71..840b7de 100644 +--- a/instrumentation/events/lttng-module/kvm.h ++++ b/instrumentation/events/lttng-module/kvm.h +@@ -86,7 +86,7 @@ LTTNG_TRACEPOINT_EVENT(kvm_ack_irq, + + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,15,0) \ + || LTTNG_KERNEL_RANGE(4,14,14, 4,15,0) \ +- || LTTNG_KERNEL_RANGE(4,9,77, 4,10,0) \ ++ || LTTNG_KERNEL_RANGE(4,7,0, 4,10,0) \ + || LTTNG_KERNEL_RANGE(4,4,112, 4,5,0) \ + || LTTNG_KERNEL_RANGE(3,16,52, 3,17,0) \ + || LTTNG_KERNEL_RANGE(3,2,97, 3,3,0)) +-- +2.11.1 + diff --git a/meta-snowyowl/recipes-kernel/lttng/lttng-modules/0002-Fix-kvm-instrumentation-for-4.15.patch b/meta-snowyowl/recipes-kernel/lttng/lttng-modules/0002-Fix-kvm-instrumentation-for-4.15.patch new file mode 100644 index 00000000..0978ecb4 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/lttng/lttng-modules/0002-Fix-kvm-instrumentation-for-4.15.patch @@ -0,0 +1,28 @@ +From b1406be7b1b151f2b8e69b1de846ba444c71ca03 Mon Sep 17 00:00:00 2001 +From: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> +Date: Wed, 27 Dec 2017 09:07:30 -0500 +Subject: [PATCH 2/4] Fix: kvm instrumentation for 4.15 + +Incorrect version range. + +Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> +--- + instrumentation/events/lttng-module/kvm.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/instrumentation/events/lttng-module/kvm.h b/instrumentation/events/lttng-module/kvm.h +index c01772c..ec74bdd 100644 +--- a/instrumentation/events/lttng-module/kvm.h ++++ b/instrumentation/events/lttng-module/kvm.h +@@ -84,7 +84,7 @@ LTTNG_TRACEPOINT_EVENT(kvm_ack_irq, + { KVM_TRACE_MMIO_READ, "read" }, \ + { KVM_TRACE_MMIO_WRITE, "write" } + +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,34)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,15,0)) + + LTTNG_TRACEPOINT_EVENT(kvm_mmio, + TP_PROTO(int type, int len, u64 gpa, void *val), +-- +2.11.1 + diff --git a/meta-snowyowl/recipes-kernel/lttng/lttng-modules/0003-Update-kvm-instrumentation-for-3.16.52-and-3.2.97.patch b/meta-snowyowl/recipes-kernel/lttng/lttng-modules/0003-Update-kvm-instrumentation-for-3.16.52-and-3.2.97.patch new file mode 100644 index 00000000..177cf53b --- /dev/null +++ b/meta-snowyowl/recipes-kernel/lttng/lttng-modules/0003-Update-kvm-instrumentation-for-3.16.52-and-3.2.97.patch @@ -0,0 +1,50 @@ +From 523fd15bb1100ab9a09ca776585ecb689516c1ef Mon Sep 17 00:00:00 2001 +From: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> +Date: Tue, 2 Jan 2018 11:07:05 -0500 +Subject: [PATCH 3/4] Update: kvm instrumentation for 3.16.52 and 3.2.97 + +Starting from 3.16.52 and 3.2.97, the 3.16 and 3.2 stable kernel +branches backport a kvm instrumentation change introduced in 4.15 which +affects the prototype of the kvm_mmio event. + +Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> +--- + instrumentation/events/lttng-module/kvm.h | 8 +++++--- + 1 file changed, 5 insertions(+), 3 deletions(-) + +diff --git a/instrumentation/events/lttng-module/kvm.h b/instrumentation/events/lttng-module/kvm.h +index ec74bdd..ea63e88 100644 +--- a/instrumentation/events/lttng-module/kvm.h ++++ b/instrumentation/events/lttng-module/kvm.h +@@ -84,7 +84,9 @@ LTTNG_TRACEPOINT_EVENT(kvm_ack_irq, + { KVM_TRACE_MMIO_READ, "read" }, \ + { KVM_TRACE_MMIO_WRITE, "write" } + +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,15,0)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,15,0) \ ++ || LTTNG_KERNEL_RANGE(3,16,52, 3,17,0) \ ++ || LTTNG_KERNEL_RANGE(3,2,97, 3,3,0)) + + LTTNG_TRACEPOINT_EVENT(kvm_mmio, + TP_PROTO(int type, int len, u64 gpa, void *val), +@@ -98,7 +100,7 @@ LTTNG_TRACEPOINT_EVENT(kvm_mmio, + ) + ) + +-#else /* #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,15,0)) */ ++#else + + LTTNG_TRACEPOINT_EVENT(kvm_mmio, + TP_PROTO(int type, int len, u64 gpa, u64 val), +@@ -112,7 +114,7 @@ LTTNG_TRACEPOINT_EVENT(kvm_mmio, + ) + ) + +-#endif /* #else #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,15,0)) */ ++#endif + + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,34)) + +-- +2.11.1 + diff --git a/meta-snowyowl/recipes-kernel/lttng/lttng-modules/0004-Update-kvm-instrumentation-for-4.14.14-4.9.77-4.4.11.patch b/meta-snowyowl/recipes-kernel/lttng/lttng-modules/0004-Update-kvm-instrumentation-for-4.14.14-4.9.77-4.4.11.patch new file mode 100644 index 00000000..0a653f52 --- /dev/null +++ b/meta-snowyowl/recipes-kernel/lttng/lttng-modules/0004-Update-kvm-instrumentation-for-4.14.14-4.9.77-4.4.11.patch @@ -0,0 +1,32 @@ +From 0a128b6bc92cbc3315d4618ed8b9da37b2367573 Mon Sep 17 00:00:00 2001 +From: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> +Date: Wed, 17 Jan 2018 11:17:08 -0500 +Subject: [PATCH 4/4] Update: kvm instrumentation for 4.14.14+, 4.9.77+, + 4.4.112+ + +Starting from 3.14.14, 4.9.77, and 4.4.112, the 3.14, 4.9, and 4.4 +stable kernel branches backport a kvm instrumentation change introduced +in 4.15 which affects the prototype of the kvm_mmio event. + +Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> +--- + instrumentation/events/lttng-module/kvm.h | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/instrumentation/events/lttng-module/kvm.h b/instrumentation/events/lttng-module/kvm.h +index ea63e88..698cc71 100644 +--- a/instrumentation/events/lttng-module/kvm.h ++++ b/instrumentation/events/lttng-module/kvm.h +@@ -85,6 +85,9 @@ LTTNG_TRACEPOINT_EVENT(kvm_ack_irq, + { KVM_TRACE_MMIO_WRITE, "write" } + + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,15,0) \ ++ || LTTNG_KERNEL_RANGE(4,14,14, 4,15,0) \ ++ || LTTNG_KERNEL_RANGE(4,9,77, 4,10,0) \ ++ || LTTNG_KERNEL_RANGE(4,4,112, 4,5,0) \ + || LTTNG_KERNEL_RANGE(3,16,52, 3,17,0) \ + || LTTNG_KERNEL_RANGE(3,2,97, 3,3,0)) + +-- +2.11.1 + diff --git a/meta-snowyowl/recipes-kernel/lttng/lttng-modules_%.bbappend b/meta-snowyowl/recipes-kernel/lttng/lttng-modules_%.bbappend index 5a800608..cae9d002 100644 --- a/meta-snowyowl/recipes-kernel/lttng/lttng-modules_%.bbappend +++ b/meta-snowyowl/recipes-kernel/lttng/lttng-modules_%.bbappend @@ -1 +1,7 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" inherit kernel-openssl +SRC_URI_append_snowyowl = " file://0001-Update-kvm-instrumentation-for-4.15.patch \ + file://0002-Fix-kvm-instrumentation-for-4.15.patch \ + file://0003-Update-kvm-instrumentation-for-3.16.52-and-3.2.97.patch \ + file://0004-Update-kvm-instrumentation-for-4.14.14-4.9.77-4.4.11.patch \ + file://0001-kvm.h-workaround-kernel-version-issues.patch" |