diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/9057-amd-xgbe-For-mac-SNPSVER-0x30H-modifying-driver-to-u.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/9057-amd-xgbe-For-mac-SNPSVER-0x30H-modifying-driver-to-u.patch | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/9057-amd-xgbe-For-mac-SNPSVER-0x30H-modifying-driver-to-u.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/9057-amd-xgbe-For-mac-SNPSVER-0x30H-modifying-driver-to-u.patch new file mode 100644 index 00000000..0d034c2d --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-5.15/9057-amd-xgbe-For-mac-SNPSVER-0x30H-modifying-driver-to-u.patch @@ -0,0 +1,77 @@ +From 708136fb3bf09ba7c048dc0401ab1464afb7b97c Mon Sep 17 00:00:00 2001 +From: rgaridap <Ramesh.Garidapuri@amd.com> +Date: Fri, 15 Jul 2022 15:05:26 +0530 +Subject: [PATCH 57/57] amd-xgbe:For mac SNPSVER 0x30H modifying driver to + update tx + +flowcontrole + +Before 30H it was single register per queue but from 30H onwards there is one register per priority i.e. 8 in total + +Signed-off-by: Ajith Nayak <Ajith.Nayak@amd.com> +Change-Id: I1be23f5683167dc2ecdeac72e08f99fa0ef33cf3 +--- + drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 26 ++++++++++++++++++------ + 1 file changed, 20 insertions(+), 6 deletions(-) + +diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c +index 8e37343ef098..7171ebc3973e 100644 +--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c ++++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c +@@ -528,15 +528,22 @@ static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) + { + unsigned int max_q_count, q_count; + unsigned int reg, reg_val; +- unsigned int i; ++ unsigned int i, ver; + + /* Clear MTL flow control */ + for (i = 0; i < pdata->rx_q_count; i++) + XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); + +- /* Clear MAC flow control */ + max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; +- q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); ++ /* For ver 30H the TFCR is present per priority instead of per queue */ ++ ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); ++ if (ver >= 0x30) { ++ q_count = max_q_count; ++ } else { ++ q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); ++ } ++ ++ /* Clear MAC flow control */ + reg = MAC_Q0TFCR; + for (i = 0; i < q_count; i++) { + reg_val = XGMAC_IOREAD(pdata, reg); +@@ -555,7 +562,7 @@ static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) + struct ieee_ets *ets = pdata->ets; + unsigned int max_q_count, q_count; + unsigned int reg, reg_val; +- unsigned int i; ++ unsigned int i, ver; + + /* Set MTL flow control */ + for (i = 0; i < pdata->rx_q_count; i++) { +@@ -578,9 +585,16 @@ static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) + ehfc ? "enabled" : "disabled", i); + } + +- /* Set MAC flow control */ + max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES; +- q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); ++ /* For ver 30H the TFCR is present per priority instead of per queue */ ++ ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); ++ if (ver >= 0x30) { ++ q_count = max_q_count; ++ } else { ++ q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count); ++ } ++ ++ /* Set MAC flow control */ + reg = MAC_Q0TFCR; + for (i = 0; i < q_count; i++) { + reg_val = XGMAC_IOREAD(pdata, reg); +-- +2.37.3 + |