diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2923-drm-amdgpu-correct-programming-of-ih_chicken-for-Arc.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2923-drm-amdgpu-correct-programming-of-ih_chicken-for-Arc.patch | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2923-drm-amdgpu-correct-programming-of-ih_chicken-for-Arc.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2923-drm-amdgpu-correct-programming-of-ih_chicken-for-Arc.patch new file mode 100644 index 00000000..d2914cc7 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2923-drm-amdgpu-correct-programming-of-ih_chicken-for-Arc.patch @@ -0,0 +1,51 @@ +From 5a753a9cd45dcfb5cfcd60bbaca4589dc5691bf8 Mon Sep 17 00:00:00 2001 +From: Le Ma <le.ma@amd.com> +Date: Tue, 26 Feb 2019 20:37:17 +0800 +Subject: [PATCH 2923/2940] drm/amdgpu: correct programming of ih_chicken for + Arcturus + +ih_chicken is a register that is not allowed to access by driver +in the L0 security policy. +psp bl need to enable field to allow driver to use physical +bus address for ih ring on secure part. + +Signed-off-by: Le Ma <le.ma@amd.com> +Reviewed-by: Snow Zhang <snow.zhang@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +index 5f54acc70fec..ee9cd8579038 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c ++++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +@@ -217,7 +217,7 @@ static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih) + static int vega10_ih_irq_init(struct amdgpu_device *adev) + { + struct amdgpu_ih_ring *ih; +- u32 ih_rb_cntl; ++ u32 ih_rb_cntl, ih_chicken; + int ret = 0; + u32 tmp; + +@@ -245,6 +245,15 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) + WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); + } + ++ if (adev->asic_type == CHIP_ARCTURUS && ++ adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { ++ if (adev->irq.ih.use_bus_addr) { ++ ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); ++ ih_chicken |= 0x00000010; ++ WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); ++ } ++ } ++ + /* set the writeback address whether it's enabled or not */ + WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, + lower_32_bits(ih->wptr_addr)); +-- +2.17.1 + |