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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2916-drm-amdgpu-optimize-gfx9-init_microcode-function.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2916-drm-amdgpu-optimize-gfx9-init_microcode-function.patch325
1 files changed, 325 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2916-drm-amdgpu-optimize-gfx9-init_microcode-function.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2916-drm-amdgpu-optimize-gfx9-init_microcode-function.patch
new file mode 100644
index 00000000..f1405021
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2916-drm-amdgpu-optimize-gfx9-init_microcode-function.patch
@@ -0,0 +1,325 @@
+From cf3365675675026e8d82bebfb09c4f75783c8583 Mon Sep 17 00:00:00 2001
+From: Le Ma <le.ma@amd.com>
+Date: Tue, 18 Sep 2018 16:11:44 +0800
+Subject: [PATCH 2916/2940] drm/amdgpu: optimize gfx9 init_microcode function
+
+Split each type of firmware into single function for easy to maintain.
+
+Signed-off-by: Le Ma <le.ma@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 247 ++++++++++++++++----------
+ 1 file changed, 153 insertions(+), 94 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 5feb2b74b002..0e1caec68388 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -613,47 +613,14 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
+ }
+ }
+
+-static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
++static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev,
++ const char *chip_name)
+ {
+- const char *chip_name;
+ char fw_name[30];
+ int err;
+ struct amdgpu_firmware_info *info = NULL;
+ const struct common_firmware_header *header = NULL;
+ const struct gfx_firmware_header_v1_0 *cp_hdr;
+- const struct rlc_firmware_header_v2_0 *rlc_hdr;
+- unsigned int *tmp = NULL;
+- unsigned int i = 0;
+- uint16_t version_major;
+- uint16_t version_minor;
+- uint32_t smu_version;
+-
+- DRM_DEBUG("\n");
+-
+- switch (adev->asic_type) {
+- case CHIP_VEGA10:
+- chip_name = "vega10";
+- break;
+- case CHIP_VEGA12:
+- chip_name = "vega12";
+- break;
+- case CHIP_VEGA20:
+- chip_name = "vega20";
+- break;
+- case CHIP_RAVEN:
+- if (adev->rev_id >= 8)
+- chip_name = "raven2";
+- else if (adev->pdev->device == 0x15d8)
+- chip_name = "picasso";
+- else
+- chip_name = "raven";
+- break;
+- case CHIP_ARCTURUS:
+- chip_name = "arcturus";
+- break;
+- default:
+- BUG();
+- }
+
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
+ err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
+@@ -688,6 +655,58 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
+ adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+ adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
+
++ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
++ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
++ info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
++ info->fw = adev->gfx.pfp_fw;
++ header = (const struct common_firmware_header *)info->fw->data;
++ adev->firmware.fw_size +=
++ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
++
++ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
++ info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
++ info->fw = adev->gfx.me_fw;
++ header = (const struct common_firmware_header *)info->fw->data;
++ adev->firmware.fw_size +=
++ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
++
++ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
++ info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
++ info->fw = adev->gfx.ce_fw;
++ header = (const struct common_firmware_header *)info->fw->data;
++ adev->firmware.fw_size +=
++ ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
++ }
++
++out:
++ if (err) {
++ dev_err(adev->dev,
++ "gfx9: Failed to load firmware \"%s\"\n",
++ fw_name);
++ release_firmware(adev->gfx.pfp_fw);
++ adev->gfx.pfp_fw = NULL;
++ release_firmware(adev->gfx.me_fw);
++ adev->gfx.me_fw = NULL;
++ release_firmware(adev->gfx.ce_fw);
++ adev->gfx.ce_fw = NULL;
++ }
++ return err;
++}
++
++static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev,
++ const char *chip_name)
++{
++ char fw_name[30];
++ int err;
++ struct amdgpu_firmware_info *info = NULL;
++ const struct common_firmware_header *header = NULL;
++ const struct rlc_firmware_header_v2_0 *rlc_hdr;
++ unsigned int *tmp = NULL;
++ unsigned int i = 0;
++ uint16_t version_major;
++ uint16_t version_minor;
++ uint32_t smu_version;
++
+ /*
+ * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin
+ * instead of picasso_rlc.bin.
+@@ -762,57 +781,7 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
+ if (adev->gfx.rlc.is_rlc_v2_1)
+ gfx_v9_0_init_rlc_ext_microcode(adev);
+
+- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
+- err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
+- if (err)
+- goto out;
+- err = amdgpu_ucode_validate(adev->gfx.mec_fw);
+- if (err)
+- goto out;
+- cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
+- adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
+- adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
+-
+-
+- snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
+- err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
+- if (!err) {
+- err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
+- if (err)
+- goto out;
+- cp_hdr = (const struct gfx_firmware_header_v1_0 *)
+- adev->gfx.mec2_fw->data;
+- adev->gfx.mec2_fw_version =
+- le32_to_cpu(cp_hdr->header.ucode_version);
+- adev->gfx.mec2_feature_version =
+- le32_to_cpu(cp_hdr->ucode_feature_version);
+- } else {
+- err = 0;
+- adev->gfx.mec2_fw = NULL;
+- }
+-
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
+- info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
+- info->fw = adev->gfx.pfp_fw;
+- header = (const struct common_firmware_header *)info->fw->data;
+- adev->firmware.fw_size +=
+- ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+-
+- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
+- info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
+- info->fw = adev->gfx.me_fw;
+- header = (const struct common_firmware_header *)info->fw->data;
+- adev->firmware.fw_size +=
+- ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+-
+- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
+- info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
+- info->fw = adev->gfx.ce_fw;
+- header = (const struct common_firmware_header *)info->fw->data;
+- adev->firmware.fw_size +=
+- ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
+-
+ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
+ info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
+ info->fw = adev->gfx.rlc_fw;
+@@ -842,7 +811,58 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
+ adev->firmware.fw_size +=
+ ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
+ }
++ }
++
++out:
++ if (err) {
++ dev_err(adev->dev,
++ "gfx9: Failed to load firmware \"%s\"\n",
++ fw_name);
++ release_firmware(adev->gfx.rlc_fw);
++ adev->gfx.rlc_fw = NULL;
++ }
++ return err;
++}
++
++static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev,
++ const char *chip_name)
++{
++ char fw_name[30];
++ int err;
++ struct amdgpu_firmware_info *info = NULL;
++ const struct common_firmware_header *header = NULL;
++ const struct gfx_firmware_header_v1_0 *cp_hdr;
++
++ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
++ err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
++ if (err)
++ goto out;
++ err = amdgpu_ucode_validate(adev->gfx.mec_fw);
++ if (err)
++ goto out;
++ cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
++ adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
++ adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
++
+
++ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
++ err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
++ if (!err) {
++ err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
++ if (err)
++ goto out;
++ cp_hdr = (const struct gfx_firmware_header_v1_0 *)
++ adev->gfx.mec2_fw->data;
++ adev->gfx.mec2_fw_version =
++ le32_to_cpu(cp_hdr->header.ucode_version);
++ adev->gfx.mec2_feature_version =
++ le32_to_cpu(cp_hdr->ucode_feature_version);
++ } else {
++ err = 0;
++ adev->gfx.mec2_fw = NULL;
++ }
++
++ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
+ info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
+ info->fw = adev->gfx.mec_fw;
+@@ -871,7 +891,6 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
+ adev->firmware.fw_size +=
+ ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
+ }
+-
+ }
+
+ out:
+@@ -881,14 +900,6 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
+ dev_err(adev->dev,
+ "gfx9: Failed to load firmware \"%s\"\n",
+ fw_name);
+- release_firmware(adev->gfx.pfp_fw);
+- adev->gfx.pfp_fw = NULL;
+- release_firmware(adev->gfx.me_fw);
+- adev->gfx.me_fw = NULL;
+- release_firmware(adev->gfx.ce_fw);
+- adev->gfx.ce_fw = NULL;
+- release_firmware(adev->gfx.rlc_fw);
+- adev->gfx.rlc_fw = NULL;
+ release_firmware(adev->gfx.mec_fw);
+ adev->gfx.mec_fw = NULL;
+ release_firmware(adev->gfx.mec2_fw);
+@@ -897,6 +908,54 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
+ return err;
+ }
+
++static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
++{
++ const char *chip_name;
++ int r;
++
++ DRM_DEBUG("\n");
++
++ switch (adev->asic_type) {
++ case CHIP_VEGA10:
++ chip_name = "vega10";
++ break;
++ case CHIP_VEGA12:
++ chip_name = "vega12";
++ break;
++ case CHIP_VEGA20:
++ chip_name = "vega20";
++ break;
++ case CHIP_RAVEN:
++ if (adev->rev_id >= 8)
++ chip_name = "raven2";
++ else if (adev->pdev->device == 0x15d8)
++ chip_name = "picasso";
++ else
++ chip_name = "raven";
++ break;
++ break;
++ case CHIP_ARCTURUS:
++ chip_name = "arcturus";
++ break;
++ default:
++ BUG();
++ }
++
++ r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name);
++ if (r)
++ return r;
++
++ r = gfx_v9_0_init_rlc_microcode(adev, chip_name);
++ if (r)
++ return r;
++
++ r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name);
++ if (r)
++ return r;
++
++ return r;
++}
++
+ static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
+ {
+ u32 count = 0;
+--
+2.17.1
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-01 08:43:03 +0000