diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2899-drm-amdgpu-dynamically-initialize-IP-offset-for-Arct.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2899-drm-amdgpu-dynamically-initialize-IP-offset-for-Arct.patch | 125 |
1 files changed, 125 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2899-drm-amdgpu-dynamically-initialize-IP-offset-for-Arct.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2899-drm-amdgpu-dynamically-initialize-IP-offset-for-Arct.patch new file mode 100644 index 00000000..933307fd --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2899-drm-amdgpu-dynamically-initialize-IP-offset-for-Arct.patch @@ -0,0 +1,125 @@ +From 92d75d83366b2a087e66c2922a8d4a6f92f24b34 Mon Sep 17 00:00:00 2001 +From: Le Ma <le.ma@amd.com> +Date: Tue, 9 Jul 2019 09:21:53 -0500 +Subject: [PATCH 2899/2940] drm/amdgpu: dynamically initialize IP offset for + Arcturus + +Add support for the IP offsets on Arcturus. + +Signed-off-by: Le Ma <le.ma@amd.com> +Acked-by: Snow Zhang < Snow.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/Makefile | 3 +- + drivers/gpu/drm/amd/amdgpu/arct_reg_init.c | 57 ++++++++++++++++++++++ + drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++ + drivers/gpu/drm/amd/amdgpu/soc15.h | 1 + + 4 files changed, 63 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/amd/amdgpu/arct_reg_init.c + +diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile +index 23286ee1b587..38a0a0e8677d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/Makefile ++++ b/drivers/gpu/drm/amd/amdgpu/Makefile +@@ -66,7 +66,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce + + amdgpu-y += \ + vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \ +- vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o ++ vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \ ++ arct_reg_init.o + + # add DF block + amdgpu-y += \ +diff --git a/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c b/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c +new file mode 100644 +index 000000000000..51b8cdffb196 +--- /dev/null ++++ b/drivers/gpu/drm/amd/amdgpu/arct_reg_init.c +@@ -0,0 +1,57 @@ ++/* ++ * Copyright 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#include "amdgpu.h" ++#include "soc15.h" ++ ++#include "soc15_common.h" ++#include "soc15_hw_ip.h" ++#include "arct_ip_offset.h" ++ ++int arct_reg_base_init(struct amdgpu_device *adev) ++{ ++ /* HW has more IP blocks, only initialized the block needed by our driver */ ++ uint32_t i; ++ for (i = 0 ; i < MAX_INSTANCE ; ++i) { ++ adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); ++ adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); ++ adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); ++ adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); ++ adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); ++ adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); ++ adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); ++ adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); ++ adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); ++ adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); ++ adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); ++ adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(SDMA2_BASE.instance[i])); ++ adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(SDMA3_BASE.instance[i])); ++ adev->reg_offset[SDMA4_HWIP][i] = (uint32_t *)(&(SDMA4_BASE.instance[i])); ++ adev->reg_offset[SDMA5_HWIP][i] = (uint32_t *)(&(SDMA5_BASE.instance[i])); ++ adev->reg_offset[SDMA6_HWIP][i] = (uint32_t *)(&(SDMA6_BASE.instance[i])); ++ adev->reg_offset[SDMA7_HWIP][i] = (uint32_t *)(&(SDMA7_BASE.instance[i])); ++ adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); ++ } ++ return 0; ++} ++ ++ +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index 3b5223fca9a0..800dd76dcf92 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -585,6 +585,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) + case CHIP_VEGA20: + vega20_reg_base_init(adev); + break; ++ case CHIP_ARCTURUS: ++ arct_reg_base_init(adev); ++ break; + default: + return -EINVAL; + } +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h +index 7a6b2cc6d9f5..a3dde0c31f57 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.h ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.h +@@ -77,6 +77,7 @@ void soc15_program_register_sequence(struct amdgpu_device *adev, + + int vega10_reg_base_init(struct amdgpu_device *adev); + int vega20_reg_base_init(struct amdgpu_device *adev); ++int arct_reg_base_init(struct amdgpu_device *adev); + + void vega10_doorbell_index_init(struct amdgpu_device *adev); + void vega20_doorbell_index_init(struct amdgpu_device *adev); +-- +2.17.1 + |