diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2891-drm-amdgpu-rename-AMDGPU_GFXHUB-MMHUB-macro-with-hub.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2891-drm-amdgpu-rename-AMDGPU_GFXHUB-MMHUB-macro-with-hub.patch | 461 |
1 files changed, 461 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2891-drm-amdgpu-rename-AMDGPU_GFXHUB-MMHUB-macro-with-hub.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2891-drm-amdgpu-rename-AMDGPU_GFXHUB-MMHUB-macro-with-hub.patch new file mode 100644 index 00000000..51ec7e61 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2891-drm-amdgpu-rename-AMDGPU_GFXHUB-MMHUB-macro-with-hub.patch @@ -0,0 +1,461 @@ +From 9a4606fb494dadb1eb6398278ac821c5ec833628 Mon Sep 17 00:00:00 2001 +From: Le Ma <le.ma@amd.com> +Date: Thu, 30 Aug 2018 20:43:04 +0800 +Subject: [PATCH 2891/2940] drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with + hub number + +The number of GFXHUB/MMHUB may be expanded in later ASICs. + +Signed-off-by: Le Ma <le.ma@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Chaudhary Amit Kumar <Chaudharyamit.Kumar@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++-- + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 ++-- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 +++---- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +++---- + drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 30 ++++++++++++------------ + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 ++--- + drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- + drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++-- + drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 ++--- + drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 6 ++--- + 16 files changed, 46 insertions(+), 46 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +index 80a070081b60..5777d11443d4 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -2995,12 +2995,12 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) + switch (args->in.op) { + case AMDGPU_VM_OP_RESERVE_VMID: + /* current, we only have requirement to reserve vmid from gfxhub */ +- r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); ++ r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0); + if (r) + return r; + break; + case AMDGPU_VM_OP_UNRESERVE_VMID: +- amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB); ++ amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0); + break; + default: + return -EINVAL; +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +index a5cd3508d17c..78f2bbc243fc 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +@@ -101,8 +101,8 @@ struct amdgpu_bo_list_entry; + + /* max number of VMHUB */ + #define AMDGPU_MAX_VMHUBS 2 +-#define AMDGPU_GFXHUB 0 +-#define AMDGPU_MMHUB 1 ++#define AMDGPU_GFXHUB_0 0 ++#define AMDGPU_MMHUB_0 1 + + /* hardcode that limit for now */ + #define AMDGPU_VA_RESERVED_SIZE (1ULL << 20) +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +index e7c6fc61b237..85d33d6af5a3 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -1603,7 +1603,7 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) + /* XXX SH_MEM regs */ + /* where to put LDS, scratch, GPUVM in FSA64 space */ + mutex_lock(&adev->srbm_mutex); +- for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) { ++ for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { + nv_grbm_select(adev, 0, 0, 0, i); + /* CP and shaders */ + WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); +@@ -4984,7 +4984,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = true, +- .vmhub = AMDGPU_GFXHUB, ++ .vmhub = AMDGPU_GFXHUB_0, + .get_rptr = gfx_v10_0_ring_get_rptr_gfx, + .get_wptr = gfx_v10_0_ring_get_wptr_gfx, + .set_wptr = gfx_v10_0_ring_set_wptr_gfx, +@@ -5035,7 +5035,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = true, +- .vmhub = AMDGPU_GFXHUB, ++ .vmhub = AMDGPU_GFXHUB_0, + .get_rptr = gfx_v10_0_ring_get_rptr_compute, + .get_wptr = gfx_v10_0_ring_get_wptr_compute, + .set_wptr = gfx_v10_0_ring_set_wptr_compute, +@@ -5068,7 +5068,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = true, +- .vmhub = AMDGPU_GFXHUB, ++ .vmhub = AMDGPU_GFXHUB_0, + .get_rptr = gfx_v10_0_ring_get_rptr_compute, + .get_wptr = gfx_v10_0_ring_get_wptr_compute, + .set_wptr = gfx_v10_0_ring_set_wptr_compute, +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 06dcf8a7d3b2..8b8a42f03eec 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -1932,7 +1932,7 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev) + /* XXX SH_MEM regs */ + /* where to put LDS, scratch, GPUVM in FSA64 space */ + mutex_lock(&adev->srbm_mutex); +- for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) { ++ for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { + soc15_grbm_select(adev, 0, 0, 0, i); + /* CP and shaders */ + if (i == 0) { +@@ -5170,7 +5170,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = true, +- .vmhub = AMDGPU_GFXHUB, ++ .vmhub = AMDGPU_GFXHUB_0, + .get_rptr = gfx_v9_0_ring_get_rptr_gfx, + .get_wptr = gfx_v9_0_ring_get_wptr_gfx, + .set_wptr = gfx_v9_0_ring_set_wptr_gfx, +@@ -5221,7 +5221,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = true, +- .vmhub = AMDGPU_GFXHUB, ++ .vmhub = AMDGPU_GFXHUB_0, + .get_rptr = gfx_v9_0_ring_get_rptr_compute, + .get_wptr = gfx_v9_0_ring_get_wptr_compute, + .set_wptr = gfx_v9_0_ring_set_wptr_compute, +@@ -5256,7 +5256,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), + .support_64bit_ptrs = true, +- .vmhub = AMDGPU_GFXHUB, ++ .vmhub = AMDGPU_GFXHUB_0, + .get_rptr = gfx_v9_0_ring_get_rptr_compute, + .get_wptr = gfx_v9_0_ring_get_wptr_compute, + .set_wptr = gfx_v9_0_ring_set_wptr_compute, +diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +index 5466b0c3d2f6..052c924952b9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +@@ -357,7 +357,7 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, + + void gfxhub_v1_0_init(struct amdgpu_device *adev) + { +- struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB]; ++ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; + + hub->ctx0_ptb_addr_lo32 = + SOC15_REG_OFFSET(GC, 0, +diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c +index d605b4963f8a..8ce5bf5feb45 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c +@@ -333,7 +333,7 @@ void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, + + void gfxhub_v2_0_init(struct amdgpu_device *adev) + { +- struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB]; ++ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; + + hub->ctx0_ptb_addr_lo32 = + SOC15_REG_OFFSET(GC, 0, +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +index c377dc22e68c..8cfc3aa32391 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +@@ -61,7 +61,7 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_vmhub *hub; + u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i; + +- bits[AMDGPU_GFXHUB] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | ++ bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | +@@ -69,7 +69,7 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, + GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK; + +- bits[AMDGPU_MMHUB] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | ++ bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | + MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK | +@@ -80,39 +80,39 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev, + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + /* MM HUB */ +- hub = &adev->vmhub[AMDGPU_MMHUB]; ++ hub = &adev->vmhub[AMDGPU_MMHUB_0]; + for (i = 0; i< 16; i++) { + reg = hub->vm_context0_cntl + i; + tmp = RREG32(reg); +- tmp &= ~bits[AMDGPU_MMHUB]; ++ tmp &= ~bits[AMDGPU_MMHUB_0]; + WREG32(reg, tmp); + } + + /* GFX HUB */ +- hub = &adev->vmhub[AMDGPU_GFXHUB]; ++ hub = &adev->vmhub[AMDGPU_GFXHUB_0]; + for (i = 0; i < 16; i++) { + reg = hub->vm_context0_cntl + i; + tmp = RREG32(reg); +- tmp &= ~bits[AMDGPU_GFXHUB]; ++ tmp &= ~bits[AMDGPU_GFXHUB_0]; + WREG32(reg, tmp); + } + break; + case AMDGPU_IRQ_STATE_ENABLE: + /* MM HUB */ +- hub = &adev->vmhub[AMDGPU_MMHUB]; ++ hub = &adev->vmhub[AMDGPU_MMHUB_0]; + for (i = 0; i< 16; i++) { + reg = hub->vm_context0_cntl + i; + tmp = RREG32(reg); +- tmp |= bits[AMDGPU_MMHUB]; ++ tmp |= bits[AMDGPU_MMHUB_0]; + WREG32(reg, tmp); + } + + /* GFX HUB */ +- hub = &adev->vmhub[AMDGPU_GFXHUB]; ++ hub = &adev->vmhub[AMDGPU_GFXHUB_0]; + for (i = 0; i < 16; i++) { + reg = hub->vm_context0_cntl + i; + tmp = RREG32(reg); +- tmp |= bits[AMDGPU_GFXHUB]; ++ tmp |= bits[AMDGPU_GFXHUB_0]; + WREG32(reg, tmp); + } + break; +@@ -243,12 +243,12 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, + + mutex_lock(&adev->mman.gtt_window_lock); + +- gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB, 0); ++ gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0); + if (!adev->mman.buffer_funcs_enabled || + !adev->ib_pool_ready || + adev->asic_type > CHIP_NAVI14 || + adev->in_gpu_reset) { +- gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB, 0); ++ gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0); + mutex_unlock(&adev->mman.gtt_window_lock); + return; + } +@@ -313,7 +313,7 @@ static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid + struct amdgpu_device *adev = ring->adev; + uint32_t reg; + +- if (ring->funcs->vmhub == AMDGPU_GFXHUB) ++ if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) + reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; + else + reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; +@@ -682,8 +682,8 @@ static int gmc_v10_0_sw_init(void *handle) + * amdgpu graphics/compute will use VMIDs 1-7 + * amdkfd will use VMIDs 8-15 + */ +- adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS; +- adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS; ++ adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; ++ adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; + + amdgpu_vm_manager_init(adev); + +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index 07c1ca0b6a59..a27cfd6d1402 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -473,7 +473,7 @@ static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid, + struct amdgpu_device *adev = ring->adev; + uint32_t reg; + +- if (ring->funcs->vmhub == AMDGPU_GFXHUB) ++ if (ring->funcs->vmhub == AMDGPU_GFXHUB_0) + reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid; + else + reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid; +@@ -1075,8 +1075,8 @@ static int gmc_v9_0_sw_init(void *handle) + * amdgpu graphics/compute will use VMIDs 1-7 + * amdkfd will use VMIDs 8-15 + */ +- adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS; +- adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS; ++ adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; ++ adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS; + + amdgpu_vm_manager_init(adev); + +diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +index 59ea53900ca9..e3fc03b6a618 100644 +--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +@@ -407,7 +407,7 @@ void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) + + void mmhub_v1_0_init(struct amdgpu_device *adev) + { +- struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB]; ++ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; + + hub->ctx0_ptb_addr_lo32 = + SOC15_REG_OFFSET(MMHUB, 0, +diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c +index a5c7ed1f37eb..d2f4775299c7 100644 +--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c +@@ -324,7 +324,7 @@ void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) + + void mmhub_v2_0_init(struct amdgpu_device *adev) + { +- struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB]; ++ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0]; + + hub->ctx0_ptb_addr_lo32 = + SOC15_REG_OFFSET(MMHUB, 0, +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +index bf665bd47bf7..d962afb6d632 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +@@ -2132,7 +2132,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { + .align_mask = 0xf, + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), + .support_64bit_ptrs = true, +- .vmhub = AMDGPU_MMHUB, ++ .vmhub = AMDGPU_MMHUB_0, + .get_rptr = sdma_v4_0_ring_get_rptr, + .get_wptr = sdma_v4_0_ring_get_wptr, + .set_wptr = sdma_v4_0_ring_set_wptr, +@@ -2164,7 +2164,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = { + .align_mask = 0xf, + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), + .support_64bit_ptrs = true, +- .vmhub = AMDGPU_MMHUB, ++ .vmhub = AMDGPU_MMHUB_0, + .get_rptr = sdma_v4_0_ring_get_rptr, + .get_wptr = sdma_v4_0_page_ring_get_wptr, + .set_wptr = sdma_v4_0_page_ring_set_wptr, +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +index 89893261f145..3e536140bfd6 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +@@ -1554,7 +1554,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { + .align_mask = 0xf, + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), + .support_64bit_ptrs = true, +- .vmhub = AMDGPU_GFXHUB, ++ .vmhub = AMDGPU_GFXHUB_0, + .get_rptr = sdma_v5_0_ring_get_rptr, + .get_wptr = sdma_v5_0_ring_get_wptr, + .set_wptr = sdma_v5_0_ring_set_wptr, +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +index 74811b2aece1..2f3d4e8032d5 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +@@ -1763,7 +1763,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { + .align_mask = 0xf, + .support_64bit_ptrs = false, + .no_user_fence = true, +- .vmhub = AMDGPU_MMHUB, ++ .vmhub = AMDGPU_MMHUB_0, + .get_rptr = uvd_v7_0_ring_get_rptr, + .get_wptr = uvd_v7_0_ring_get_wptr, + .set_wptr = uvd_v7_0_ring_set_wptr, +@@ -1796,7 +1796,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { + .nop = HEVC_ENC_CMD_NO_OP, + .support_64bit_ptrs = false, + .no_user_fence = true, +- .vmhub = AMDGPU_MMHUB, ++ .vmhub = AMDGPU_MMHUB_0, + .get_rptr = uvd_v7_0_enc_ring_get_rptr, + .get_wptr = uvd_v7_0_enc_ring_get_wptr, + .set_wptr = uvd_v7_0_enc_ring_set_wptr, +diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +index e267b073f525..93d80ef17685 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +@@ -1070,7 +1070,7 @@ static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = { + .nop = VCE_CMD_NO_OP, + .support_64bit_ptrs = false, + .no_user_fence = true, +- .vmhub = AMDGPU_MMHUB, ++ .vmhub = AMDGPU_MMHUB_0, + .get_rptr = vce_v4_0_ring_get_rptr, + .get_wptr = vce_v4_0_ring_get_wptr, + .set_wptr = vce_v4_0_ring_set_wptr, +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +index 855b1f9609e4..09dc9c87ebd1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +@@ -2198,7 +2198,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { + .align_mask = 0xf, + .support_64bit_ptrs = false, + .no_user_fence = true, +- .vmhub = AMDGPU_MMHUB, ++ .vmhub = AMDGPU_MMHUB_0, + .get_rptr = vcn_v1_0_dec_ring_get_rptr, + .get_wptr = vcn_v1_0_dec_ring_get_wptr, + .set_wptr = vcn_v1_0_dec_ring_set_wptr, +@@ -2232,7 +2232,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { + .nop = VCN_ENC_CMD_NO_OP, + .support_64bit_ptrs = false, + .no_user_fence = true, +- .vmhub = AMDGPU_MMHUB, ++ .vmhub = AMDGPU_MMHUB_0, + .get_rptr = vcn_v1_0_enc_ring_get_rptr, + .get_wptr = vcn_v1_0_enc_ring_get_wptr, + .set_wptr = vcn_v1_0_enc_ring_set_wptr, +@@ -2264,7 +2264,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_jpeg_ring_vm_funcs = { + .nop = PACKET0(0x81ff, 0), + .support_64bit_ptrs = false, + .no_user_fence = true, +- .vmhub = AMDGPU_MMHUB, ++ .vmhub = AMDGPU_MMHUB_0, + .extra_dw = 64, + .get_rptr = vcn_v1_0_jpeg_ring_get_rptr, + .get_wptr = vcn_v1_0_jpeg_ring_get_wptr, +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +index 70c071d52149..84e6ee48670c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +@@ -2131,7 +2131,7 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { + static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCN_DEC, + .align_mask = 0xf, +- .vmhub = AMDGPU_MMHUB, ++ .vmhub = AMDGPU_MMHUB_0, + .get_rptr = vcn_v2_0_dec_ring_get_rptr, + .get_wptr = vcn_v2_0_dec_ring_get_wptr, + .set_wptr = vcn_v2_0_dec_ring_set_wptr, +@@ -2162,7 +2162,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCN_ENC, + .align_mask = 0x3f, + .nop = VCN_ENC_CMD_NO_OP, +- .vmhub = AMDGPU_MMHUB, ++ .vmhub = AMDGPU_MMHUB_0, + .get_rptr = vcn_v2_0_enc_ring_get_rptr, + .get_wptr = vcn_v2_0_enc_ring_get_wptr, + .set_wptr = vcn_v2_0_enc_ring_set_wptr, +@@ -2191,7 +2191,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = { + static const struct amdgpu_ring_funcs vcn_v2_0_jpeg_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCN_JPEG, + .align_mask = 0xf, +- .vmhub = AMDGPU_MMHUB, ++ .vmhub = AMDGPU_MMHUB_0, + .get_rptr = vcn_v2_0_jpeg_ring_get_rptr, + .get_wptr = vcn_v2_0_jpeg_ring_get_wptr, + .set_wptr = vcn_v2_0_jpeg_ring_set_wptr, +-- +2.17.1 + |