diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2830-drm-amdgpu-psp11-simplify-the-ucode-register-logic.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2830-drm-amdgpu-psp11-simplify-the-ucode-register-logic.patch | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2830-drm-amdgpu-psp11-simplify-the-ucode-register-logic.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2830-drm-amdgpu-psp11-simplify-the-ucode-register-logic.patch new file mode 100644 index 00000000..80ab3c56 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2830-drm-amdgpu-psp11-simplify-the-ucode-register-logic.patch @@ -0,0 +1,51 @@ +From 6c42a6eb04671ff9b308d6914f41f6ab15ba7a2e Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Sat, 6 Jul 2019 01:10:58 -0500 +Subject: [PATCH 2830/2940] drm/amdgpu/psp11: simplify the ucode register logic + +Split it between navi10 and newer and everything before +navi10. + +Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 12 ++++-------- + 1 file changed, 4 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +index fa1697617ae3..f32abfa579ac 100644 +--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c +@@ -548,12 +548,10 @@ psp_v11_0_sram_map(struct amdgpu_device *adev, + + case AMDGPU_UCODE_ID_RLC_G: + *sram_offset = 0x2000; +- if (adev->asic_type != CHIP_NAVI10 && +- adev->asic_type != CHIP_NAVI14) { ++ if (adev->asic_type < CHIP_NAVI10) { + *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA); +- } +- else { ++ } else { + *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_ADDR_NV10; + *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmRLC_GPM_UCODE_DATA_NV10; + } +@@ -561,12 +559,10 @@ psp_v11_0_sram_map(struct amdgpu_device *adev, + + case AMDGPU_UCODE_ID_SDMA0: + *sram_offset = 0x0; +- if (adev->asic_type != CHIP_NAVI10 && +- adev->asic_type != CHIP_NAVI14) { ++ if (adev->asic_type < CHIP_NAVI10) { + *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR); + *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA); +- } +- else { ++ } else { + *sram_addr_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_ADDR_NV10; + *sram_data_reg_offset = adev->reg_offset[GC_HWIP][0][1] + mmSDMA0_UCODE_DATA_NV10; + } +-- +2.17.1 + |