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-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2655-drm-amd-display-add-NAVI14-in-resource-construct.patch69
1 files changed, 69 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2655-drm-amd-display-add-NAVI14-in-resource-construct.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2655-drm-amd-display-add-NAVI14-in-resource-construct.patch
new file mode 100644
index 00000000..3f222b2a
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2655-drm-amd-display-add-NAVI14-in-resource-construct.patch
@@ -0,0 +1,69 @@
+From cfac3c36b9cd33b6cbe3b5b246bd0d52d7e15b76 Mon Sep 17 00:00:00 2001
+From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Date: Tue, 26 Feb 2019 14:38:59 -0500
+Subject: [PATCH 2655/2940] drm/amd/display: add NAVI14 in resource construct
+
+Change the pipes to 5 if the asic is nv14
+
+This is a temp patch, there was some refactor in the dml part of the code.
+which is not in this branch. for now this is good, we can implement this
+properly once we have an updated branch.
+
+Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ .../drm/amd/display/dc/dcn20/dcn20_resource.c | 23 +++++++++++++++----
+ 1 file changed, 19 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+index fa4f378efe5b..c3911501a2c0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+@@ -693,6 +693,16 @@ static const struct dc_plane_cap plane_cap = {
+ .fp16 = 1
+ }
+ };
++static const struct resource_caps res_cap_nv14 = {
++ .num_timing_generator = 5,
++ .num_opp = 5,
++ .num_video_plane = 5,
++ .num_audio = 6,
++ .num_stream_encoder = 5,
++ .num_pll = 5,
++ .num_dwb = 1,
++ .num_ddc = 5,
++};
+
+ static const struct dc_debug_options debug_defaults_drv = {
+ .disable_dmcu = true,
+@@ -2866,17 +2876,22 @@ static bool construct(
+ struct irq_service_init_data init_data;
+
+ ctx->dc_bios->regs = &bios_regs;
+-
+- pool->base.res_cap = &res_cap_nv10;
+ pool->base.funcs = &dcn20_res_pool_funcs;
+
++ if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
++ pool->base.res_cap = &res_cap_nv14;
++ pool->base.pipe_count = 5;
++ pool->base.mpcc_count = 5;
++ } else {
++ pool->base.res_cap = &res_cap_nv10;
++ pool->base.pipe_count = 6;
++ pool->base.mpcc_count = 6;
++ }
+ /*************************************************
+ * Resource + asic cap harcoding *
+ *************************************************/
+ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
+
+- pool->base.pipe_count = 6;
+- pool->base.mpcc_count = 6;
+ dc->caps.max_downscale_ratio = 200;
+ dc->caps.i2c_speed_in_khz = 100;
+ dc->caps.max_cursor_size = 256;
+--
+2.17.1
+