diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2645-drm-amdgpu-gfx10-fix-programming-of-SC_HIZ_TILE_FIFO.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2645-drm-amdgpu-gfx10-fix-programming-of-SC_HIZ_TILE_FIFO.patch | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2645-drm-amdgpu-gfx10-fix-programming-of-SC_HIZ_TILE_FIFO.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2645-drm-amdgpu-gfx10-fix-programming-of-SC_HIZ_TILE_FIFO.patch new file mode 100644 index 00000000..bd9b3699 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2645-drm-amdgpu-gfx10-fix-programming-of-SC_HIZ_TILE_FIFO.patch @@ -0,0 +1,36 @@ +From f1cf138d867411f220d694a272b07352f68edb6f Mon Sep 17 00:00:00 2001 +From: Jack Xiao <Jack.Xiao@amd.com> +Date: Tue, 28 May 2019 13:27:11 +0800 +Subject: [PATCH 2645/2940] drm/amdgpu/gfx10: fix programming of + SC_HIZ_TILE_FIFO_SIZE field + +max fifo size is 128 and PA_SC_FIFO_SIZE[20:15]=SC_HIZ_TILE_FIFO_SIZE +field is programmed in units of two entries, but 6 bits is insufficient +to hold value 128/2 = 64, so set this field as 0 which is interpreted by +the hardware as maximum physical fifo size(128). + +Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> +Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +index 4b44e87f6a0d..772437cd27b3 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -1089,7 +1089,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) + adev->gfx.config.max_hw_contexts = 8; + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; +- adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; ++ adev->gfx.config.sc_hiz_tile_fifo_size = 0x0; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; + gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); + break; +-- +2.17.1 + |