diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2617-drm-amdgpu-gfx10-use-reset-default-for-PA_SC_FIFO_SI.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2617-drm-amdgpu-gfx10-use-reset-default-for-PA_SC_FIFO_SI.patch | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2617-drm-amdgpu-gfx10-use-reset-default-for-PA_SC_FIFO_SI.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2617-drm-amdgpu-gfx10-use-reset-default-for-PA_SC_FIFO_SI.patch new file mode 100644 index 00000000..c2e5c45a --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2617-drm-amdgpu-gfx10-use-reset-default-for-PA_SC_FIFO_SI.patch @@ -0,0 +1,46 @@ +From cb1bc9866d65f4a83af41be7a549ebdd81b6e56d Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Mon, 1 Jul 2019 08:39:19 -0500 +Subject: [PATCH 2617/2940] drm/amdgpu/gfx10: use reset default for + PA_SC_FIFO_SIZE + +Recommended by the hw team. + +Reviewed-and-Tested-by: Huang Rui <ray.huang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 18 ------------------ + 1 file changed, 18 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +index f0e62853bf2f..2be389992506 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -1544,24 +1544,6 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) + + gfx_v10_0_init_compute_vmid(adev); + +- mutex_lock(&adev->grbm_idx_mutex); +- /* +- * making sure that the following register writes will be broadcasted +- * to all the shaders +- */ +- gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); +- +- tmp = REG_SET_FIELD(0, PA_SC_FIFO_SIZE, SC_FRONTEND_PRIM_FIFO_SIZE, +- adev->gfx.config.sc_prim_fifo_size_frontend); +- tmp = REG_SET_FIELD(tmp, PA_SC_FIFO_SIZE, SC_BACKEND_PRIM_FIFO_SIZE, +- adev->gfx.config.sc_prim_fifo_size_backend); +- tmp = REG_SET_FIELD(tmp, PA_SC_FIFO_SIZE, SC_HIZ_TILE_FIFO_SIZE, +- adev->gfx.config.sc_hiz_tile_fifo_size); +- tmp = REG_SET_FIELD(tmp, PA_SC_FIFO_SIZE, SC_EARLYZ_TILE_FIFO_SIZE, +- adev->gfx.config.sc_earlyz_tile_fifo_size); +- WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE, tmp); +- +- mutex_unlock(&adev->grbm_idx_mutex); + } + + static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, +-- +2.17.1 + |