diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2616-drm-amdgpu-gfx9-use-reset-default-for-PA_SC_FIFO_SIZ.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2616-drm-amdgpu-gfx9-use-reset-default-for-PA_SC_FIFO_SIZ.patch | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2616-drm-amdgpu-gfx9-use-reset-default-for-PA_SC_FIFO_SIZ.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2616-drm-amdgpu-gfx9-use-reset-default-for-PA_SC_FIFO_SIZ.patch new file mode 100644 index 00000000..421030ff --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2616-drm-amdgpu-gfx9-use-reset-default-for-PA_SC_FIFO_SIZ.patch @@ -0,0 +1,47 @@ +From 60a7ae4bd88da3f7f5ed6917472f5c5a6333bcbe Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Mon, 1 Jul 2019 08:38:12 -0500 +Subject: [PATCH 2616/2940] drm/amdgpu/gfx9: use reset default for + PA_SC_FIFO_SIZE + +Recommended by the hw team. + +Reviewed-and-Tested-by: Huang Rui <ray.huang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 19 ------------------- + 1 file changed, 19 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index ac426b833ec1..00617a655e8a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -1960,25 +1960,6 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev) + mutex_unlock(&adev->srbm_mutex); + + gfx_v9_0_init_compute_vmid(adev); +- +- mutex_lock(&adev->grbm_idx_mutex); +- /* +- * making sure that the following register writes will be broadcasted +- * to all the shaders +- */ +- gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); +- +- WREG32_SOC15_RLC(GC, 0, mmPA_SC_FIFO_SIZE, +- (adev->gfx.config.sc_prim_fifo_size_frontend << +- PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | +- (adev->gfx.config.sc_prim_fifo_size_backend << +- PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | +- (adev->gfx.config.sc_hiz_tile_fifo_size << +- PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | +- (adev->gfx.config.sc_earlyz_tile_fifo_size << +- PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); +- mutex_unlock(&adev->grbm_idx_mutex); +- + } + + static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) +-- +2.17.1 + |