diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2539-drm-amd-display-add-null-checks-and-set-update-flags.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2539-drm-amd-display-add-null-checks-and-set-update-flags.patch | 112 |
1 files changed, 112 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2539-drm-amd-display-add-null-checks-and-set-update-flags.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2539-drm-amd-display-add-null-checks-and-set-update-flags.patch new file mode 100644 index 00000000..30d88f9c --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2539-drm-amd-display-add-null-checks-and-set-update-flags.patch @@ -0,0 +1,112 @@ +From bb9ce20060305691cb76c2a92d0c5f9819422a75 Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Mon, 8 Apr 2019 14:56:29 -0400 +Subject: [PATCH 2539/2940] drm/amd/display: add null checks and set update + flags for DCN2 + +* add plane state null checks +* add and set update surface flags +* +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++ + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 8 +++----- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h | 14 +++++++++++--- + .../gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 1 - + 4 files changed, 17 insertions(+), 9 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index ddd7899b503e..02539f20d510 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1439,6 +1439,9 @@ static enum surface_update_type det_surface_update(const struct dc *dc, + + update_flags->raw = 0; // Reset all flags + ++ if (u->flip_addr) ++ update_flags->bits.addr_update = 1; ++ + if (!is_surface_in_context(context, u->surface)) { + update_flags->bits.new_plane = 1; + return UPDATE_TYPE_FULL; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +index ea56f15a51fb..f9b0ea75eeb4 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +@@ -492,7 +492,7 @@ static void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) + } + + +-static void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) ++void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) + { + DC_LOGGER_INIT(dc->ctx->logger); + +@@ -501,8 +501,6 @@ static void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) + + dcn20_plane_atomic_disable(dc, pipe_ctx); + +- //apply_DEGVIDCN10_253_wa(dc); +- + DC_LOG_DC("Power down front end %d\n", + pipe_ctx->pipe_idx); + } +@@ -1092,7 +1090,7 @@ static void dcn20_power_on_plane( + } + } + +-static void dcn20_enable_plane( ++void dcn20_enable_plane( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_state *context) +@@ -1167,7 +1165,7 @@ static void dcn20_enable_plane( + } + + +-void dcn20_program_pipe( ++static void dcn20_program_pipe( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_state *context) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h +index 78a6477deffb..2b0409454073 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h +@@ -89,7 +89,15 @@ void dcn20_pipe_control_lock_global( + struct pipe_ctx *pipe, + bool lock); + void dcn20_setup_gsl_group_as_lock(const struct dc *dc, +- struct pipe_ctx *pipe_ctx, +- bool enable); +- ++ struct pipe_ctx *pipe_ctx, ++ bool enable); ++void dcn20_pipe_control_lock( ++ struct dc *dc, ++ struct pipe_ctx *pipe, ++ bool lock); ++void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx); ++void dcn20_enable_plane( ++ struct dc *dc, ++ struct pipe_ctx *pipe_ctx, ++ struct dc_state *context); + #endif /* __DC_HWSS_DCN20_H__ */ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index ca5a7791d080..e7a8a13a9d33 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -2340,7 +2340,6 @@ bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, + context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml, + &context->res_ctx.pipe_ctx[i].rq_regs, + pipes[pipe_idx].pipe); +- + pipe_idx++; + } + +-- +2.17.1 + |