diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2531-drm-amd-display-fix-macro_tile_size-for-tiling.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2531-drm-amd-display-fix-macro_tile_size-for-tiling.patch | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2531-drm-amd-display-fix-macro_tile_size-for-tiling.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2531-drm-amd-display-fix-macro_tile_size-for-tiling.patch new file mode 100644 index 00000000..674cead2 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.19.8/2531-drm-amd-display-fix-macro_tile_size-for-tiling.patch @@ -0,0 +1,42 @@ +From 4ee3a0d21d1d52447b53cfc357367e5dba690cb4 Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Mon, 22 Apr 2019 15:38:09 -0400 +Subject: [PATCH 2531/2940] drm/amd/display: fix macro_tile_size for tiling + +A regression was introduced when we set correct tile size +for the gfx9 swizzle mode. This resulted in incorrect +macro tile size. + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +index 1daf4029b566..0bd0b5279c18 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -1753,8 +1753,6 @@ int dcn20_populate_dml_pipes_from_context( + struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state; + struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; + +- pipes[pipe_cnt].pipe.src.macro_tile_size = +- swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); + pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate; + pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe + && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln) +@@ -1818,6 +1816,8 @@ int dcn20_populate_dml_pipes_from_context( + pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps; + pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c; + ++ pipes[pipe_cnt].pipe.src.macro_tile_size = ++ swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); + swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, + &pipes[pipe_cnt].pipe.src.sw_mode); + +-- +2.17.1 + |